Radxa Zero not booting from SD card

I have a Radxa Zero V1.5 board with 512Mb ram and no eMMC.

I tried about 6 or 7 Armbian Bullseye and buster images from Radxa repository and also armbian Jammy and same problem.

I have tried multiple known working SD cards and the same problem.

It seems to get to U-boot and then just restarts in endless loop.
The log file for those will be 1st.

I also read this post:
https://forum.radxa.com/t/radxa-zero-model-ram-512m-not-boot/7348

I tried the image linked in that post and it didnt work, either.
Armbian_21.08.0-trunk_Radxa-zero_focal_current_5.10.58_xfce_desktop.img.xz

I will post the log from that also:

Any help would be appreciated.




Here is Serial log 1:
from using current builds.



G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0
l2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
S1:00000000
B2:00002000
B1:e0f83180

TE: 378506

BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz

Board ID = 2
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
board id: 2
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 792MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 792MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==256 ps 13
TxDqDly_Margin_A0==256 ps 13
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==32
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

channel==1
RxClkDly_Margin_A0==236 ps 12
TxDqDly_Margin_A0==256 ps 13
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==30
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 0000001a 0000001c 0000001d 0000001c 0000001b 0000001b 0000001a 0000001d 0000001a 0000001c 0000001b 0000001a 0000001b 0000001c 0000001c 0000001d 00000019 00000018 00000018 0000001b 00000019 00000019 00000017 0000001a 00000017 0000001a 0000001a 0000001a 00000019 00000019 00000017 00000019 dram_vref_reg_value 0x 00000057
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:53:31
auto size-- 65535DDR cs0 size: 512MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002aDDR size: 512MB
cs0 DataBus test pass
cs0 AddrBus test pass

100bdlr_step_size ps== 474
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x00094000, part: 0
bl2z: ptr: 05129330, size: 00001e40
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
OPS=0x30
ring efuse init
28 0c 30 00 01 04 18 00 00 19 35 36 32 43 46 50
[0.017150 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:57:33, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast

U-Boot 2021.07-armbian (Nov 14 2021 - 14:28:29 +0000) radxa-zero

Model: Radxa Zero
SoC: Amlogic Meson G12A (S905Y2) Revision 28:c (30:2)
DRAM: 512 MiB
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from nowhere… OK
In: serial
Out: serial
Err: serial
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0
Card did not respond to voltage select! : -110
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1…
Found U-Boot script /boot/boot.scr
7895 bytes read in 3 ms (2.5 MiB/s)

Executing script at 08000000

U-boot default fdtfile: amlogic/meson-g12a-radxa-zero.dtb
Current variant:
** Reading file would overwrite reserved memory **
Failed to load ‘/boot/armbianEnv.txt’
“Synchronous Abort” handler, esr 0x96000010
elr: 000000000105f0b0 lr : 000000000105d284 (reloc)
elr: 000000001dfb30b0 lr : 000000001dfb1284
x0 : 000000001bf74470 x1 : 0000000032000000
x2 : 0000000000001ed7 x3 : 0000000000000000
x4 : 0000000000001ed7 x5 : 0000000000000000
x6 : 0000000000000682 x7 : 0000000000000000
x8 : 0000000000000010 x9 : 0000000000000008
x10: 0000000000000044 x11: 000000001bf3e23c
x12: 0000000000000670 x13: 000000001bf3e25c
x14: 0000000000000000 x15: 000000001bf405b0
x16: 000000001df63690 x17: 0000000000000000
x18: 000000001bf51dd0 x19: 0000000000000000
x20: 0000000032000000 x21: 000000001bf74470
x22: 0000000000000000 x23: 000000001dfd8a70
x24: 0000000000000000 x25: 0000000000000001
x26: 000000000000000a x27: 0000000000000000
x28: 0000000000001ed7 x29: 000000001bf3e350

Code: d2800003 eb03005f 540001c1 d65f03c0 (f8636824)
Resetting CPU …

resetting …
bl31 reboot reason: 0xd
bl31 reboot reason: 0x0
system cmd 1.
G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0




Here is Serial log 2:
using the image linked on this post:
Radxa zero model RAM 512M not boot
Armbian_21.08.0-trunk_Radxa-zero_focal_current_5.10.58_xfce_desktop.img.xz



G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:800;NAND:81;SD?:0;SD:0;READ:0;0.0
l2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02

no sdio debug board detected
L0:00000000
L1:00000703
L2:00008067
L3:04000000
S1:00000000
B2:00002000
B1:e0f83180

TE: 375170

BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz

Board ID = 2
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
board id: 2
Load FIP HDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from SD, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from SD, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
fastboot data verify
verify result: 266
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 792MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : ERROR : Training has failed!
1D training failed
Cfg max: 2, cur: 2. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 792MHz
Load ddrfw from SD, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from SD, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==256 ps 13
TxDqDly_Margin_A0==256 ps 13
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==32
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

channel==1
RxClkDly_Margin_A0==236 ps 12
TxDqDly_Margin_A0==256 ps 13
RxClkDly_Margin_A1==0 ps 0
TxDqDly_Margin_A1==0 ps 0
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==0
VrefDac_Margin_A0==31
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==0
DeviceVref_Margin_A1==0

dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 0000001a 0000001b 0000001d 0000001b 0000001b 0000001b 0000001a 0000001d 00000019 0000001c 0000001a 0000001a 0000001a 0000001c 0000001c 0000001d 0000001a 00000019 00000019 0000001b 0000001a 0000001b 00000018 0000001a 00000017 0000001b 0000001b 0000001b 00000019 0000001a 00000019 00000019 dram_vref_reg_value 0x 00000059
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:53:31
auto size-- 65535DDR cs0 size: 512MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002aDDR size: 512MB
cs0 DataBus test pass
cs0 AddrBus test pass

100bdlr_step_size ps== 489
result report
boot times 0Enable ddr reg access
Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from SD, src: 0x0006c200, des: 0x0175c000, size: 0x000a0000, part: 0
bl2z: ptr: 05129330, size: 00001e40
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
OPS=0x30
ring efuse init
28 0c 30 00 01 04 18 00 00 19 35 36 32 43 46 50
[0.017150 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE: BL31: v1.3(release):4fc40b1
NOTICE: BL31: Built : 15:57:33, May 22 2019
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast

U-Boot 2021.04-armbian (Aug 13 2021 - 07:09:10 +0000) radxazero

Model: Radxa Zero
SoC: Amlogic Meson G12A (Unknown) Revision 28:c (30:2)
DRAM: 512 MiB
MMC: sd@ffe03000: 0, sd@ffe05000: 1, mmc@ffe07000: 2
Loading Environment from MMC… Card did not respond to voltage select! : -110
*** Warning - No block device, using default environment

In: serial@3000
Out: serial@3000
Err: serial@3000
Net: Net Initialization Skipped
No ethernet found.

Error: “load_logo” not defined

Hit any key to stop autoboot: 0
Card did not respond to voltage select! : -110
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1…
Found U-Boot script /boot/boot.scr
7622 bytes read in 3 ms (2.4 MiB/s)

Executing script at 08000000

U-boot default fdtfile: amlogic/meson-g12a-radxa-zero.dtb
Current variant:
** Reading file would overwrite reserved memory **
Failed to load ‘/boot/armbianEnv.txt’
“Synchronous Abort” handler, esr 0x96000010
elr: 000000000106b62c lr : 000000000106980c (reloc)
elr: 000000001dfab62c lr : 000000001dfa980c
x0 : 000000001bf54eb0 x1 : 0000000032000000
x2 : 0000000000001dc6 x3 : 0000000000000000
x4 : 0000000000001dc6 x5 : 0000000000000000
x6 : 0000000000000682 x7 : 0000000000000000
x8 : 0000000000000010 x9 : 0000000000000008
x10: 0000000000000044 x11: 000000001bf1bcbc
x12: 0000000000000684 x13: 000000001bf1bcdc
x14: 0000000000000000 x15: 000000001bf1e050
x16: 000000001df51268 x17: 0000000000000000
x18: 000000001bf2fdd0 x19: 0000000000000000
x20: 0000000032000000 x21: 000000001bf54eb0
x22: 0000000000000000 x23: 000000001dfd75b8
x24: 0000000000000000 x25: 0000000000000001
x26: 000000000000000a x27: 0000000000000000
x28: 0000000000001dc6 x29: 000000001bf1bdf0

Code: d2800003 eb03005f 540001c1 d65f03c0 (f8636824)
Resetting CPU …

resetting …
Rebooting with reason: 0x1
bl31 reboot reason: 0xd
bl31 reboot reason: 0x1
system cmd 1.

When did you purchase your Zero and do you happen to have the batch number for it?

I just purchased it recently from Mii Store on Aliexpress.

I don’t know where to look for a batch number. All I see on the silkscreen is Radxa Zero V1.51 and a date code 2021.11.10

Try with images start with radxa instead from https://github.com/radxa-build/radxa-zero/releases/tag/20220801-0213. Those start with armbian are unofficial.

I have the same type of board (Radxa Zero with 512M w/o EMMC) and it doesn’t boot with major distros like as Armbian or DietPi.

There are two problems in the U-boot script:

  1. Incorrect boot partition link for uSD card
  2. Incorrect memory mapping for 512M boards.

Using working script from Radxa’s ubuntu images I fixed the script for latest DietPi (works both for Bullseye and Bookworm).

Replace boot.cmd with the script bottom and recompile it with command mkimage -C none -A arm64 -T script -d /boot/boot.cmd /boot/boot.scr

DO NOT EDIT THIS FILE

Please edit /boot/dietpiEnv.txt to set supported parameters

If you must, edit /boot/boot.cmd and recompile /boot/boot.scr with:

mkimage -C none -A arm64 -T script -d /boot/boot.cmd /boot/boot.scr

Default values

setenv rootdev “/dev/mmcblk1p0”
setenv rootfstype “ext4”
setenv consoleargs “console=tty1”
setenv verbosity “4”
setenv docker_optimizations “off”
setenv overlay_path “amlogic”
setenv overlay_prefix “meson”

Load addresses

setenv scriptaddr “0x32000000”
setenv kernel_addr_r “0x34000000”
setenv fdt_addr_r “0x4080000”
setenv overlay_error “false”

fix zero 512M

setenv dtb_mem_addr “0x01000000”
setenv fdt_addr_r “0x08008000”
setenv fdtoverlay_addr_r “0x01000000”
setenv initrd_start “0x13000000”
setenv kernel_addr_r “0x08080000”
setenv loadaddr “0x01080000”
setenv pxefile_addr_r “0x01080000”
setenv ramdisk_addr_r “0x13000000”
setenv scriptaddr “0x08000000”

Load dietpiEnv.txt

if test -e ${devtype} ${devnum} ${prefix}dietpiEnv.txt; then
load ${devtype} ${devnum} ${scriptaddr} ${prefix}dietpiEnv.txt
env import -t ${scriptaddr} ${filesize}
fi

Define kernel command-line arguments

setenv bootargs “root=${rootdev} rootfstype=${rootfstype} rootwait ${consoleargs} loglevel=${verbosity} consoleblank=0 coherent_pool=2M usb-storage.quirks=${usbstoragequirks} ${extraargs}”

Add bootargs for Docker

if test “${docker_optimizations}” = “on”; then setenv bootargs “${bootargs} cgroup_enable=memory swapaccount=1”; fi

Load kernel, initramfs and device tree

load ${devtype} ${devnum} ${kernel_addr_r} ${prefix}Image
load ${devtype} ${devnum} ${ramdisk_addr_r} ${prefix}uInitrd
load ${devtype} ${devnum} ${fdt_addr_r} ${prefix}dtb/${fdtfile}
fdt addr ${fdt_addr_r}

Apply DT overlays

if test -n “${overlays}” || test -n “${user_overlays}”; then
fdt resize 65536
for overlay_file in ${overlays}; do
if load ${devtype} ${devnum} ${scriptaddr} ${prefix}dtb/${overlay_path}/overlay/${overlay_prefix}-${overlay_file}.dtbo; then
echo “Applying kernel provided DT overlay ${overlay_prefix}-${overlay_file}.dtbo”
fdt apply ${scriptaddr} || setenv overlay_error “true”
fi
done

for overlay_file in ${user_overlays}; do
	if load ${devtype} ${devnum} ${scriptaddr} ${prefix}overlay-user/${overlay_file}.dtbo; then
		echo "Applying user provided DT overlay ${overlay_file}.dtbo"
		fdt apply ${scriptaddr} || setenv overlay_error "true"
	fi
done

if test "${overlay_error}" = "true"; then
	echo "Error applying DT overlays, restoring original DT"
	load ${devtype} ${devnum} ${fdt_addr_r} ${prefix}dtb/${fdtfile}
else
	if load ${devtype} ${devnum} ${scriptaddr} ${prefix}dtb/${overlay_path}/overlay/${overlay_prefix}-fixup.scr; then
		echo "Applying kernel provided DT fixup script (${overlay_prefix}-fixup.scr)"
		source ${scriptaddr}
	fi
	if test -e ${devtype} ${devnum} ${prefix}fixup.scr; then
		load ${devtype} ${devnum} ${scriptaddr} ${prefix}fixup.scr
		echo "Applying user provided fixup script (fixup.scr)"
		source ${scriptaddr}
	fi
fi

fi

Boot

booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}