The CLK frequency for communicating with the eMMC card is set incorrectly

am currently working with a Chinese rockchip rk3568 processor and an emmc interface. I have studied the source codes of such large projects as Linux and U-boot for this interface, and I think I have practically reproduced the same actions as there (in both projects, initialization on bare hardware is very similar). However, unlike the sources, I have a problem with the CLK clock signal. It seems logical to me that the processor takes a certain frequency (freq_1) and feeds it to the clocking of the eMMC peripheral device (of course, we set the source of this frequency through the processor’s system registers). Inside the periphery itself, we set up dividers and turn on CLK clock signals, and as a result, at the output we have to divide the CLK frequency that we expect. I checked the registers, I really write the value of the divider there, and the frequency stability bit is set as required. But my problem is that the periphery seems to ignore these dividers and I see the same frequency at the output as at the input (freq_1). Maybe the whole point is that I’m doing something earlier (or later) than I should, but I don’t understand what. I will be grateful for any help

I found out experimentally that CLK line clocking for eMMC is configured directly through the system registers (CRU_CLKSEL_CON28). That is, the peripheral supports only those values that are available in this register. Thus, U-boot never adjusts the dividers in the eMMC peripheral register (Clock Control Register) and everything works correctly.
If you rigidly force U-boot to set the divider in the register, then the output frequency will still be equal to the input.
At the moment, based on the results of experiments, I conclude that for some reason Rockchip has not implemented (?) the operation of dividers in the eMMC block