第一次成功刷了udisk-loader後刷Armbian開機失敗
第二次從頭來過，結果boot-g12刷任何bootloader全失敗
其中radxa-zero-erase-emmc.bin 大概到seq=4的時候會在_writeAMLCData, line 416的地方失敗
offset=294912, AMLC dataSize=49152
serial port tx/rx接反，有一些輸出
之後再來補上
EMMC:
SEC 219
B041
KLMBG2JETD
Radxa Zero刷成磚，USB可識別寫入bootloader失敗
bl2_stage_init 0x81
hw id: 0x0001 - pwm id 0x00
bl2_stage_init 0xc0
bl2_stage_init 0x02
L0:00000000
L1:00000703
L2:00008067
L3:04000000
S1:00000000
B2:00002000
B1:e0f83180
TE: 154126
BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
Board ID = 2
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
board id: 2
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
00000000
emmc switch 1 ok
00000000
emmc switch 2 ok
fastboot data verify
verify result: 265
Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 792MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0
00000000
emmc switch 0 ok
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
channel==0
RxClkDly_Margin_A0==216 ps 11
TxDqDly_Margin_A0==216 ps 11
RxClkDly_Margin_A1==197 ps 10
TxDqDly_Margin_A1==216 ps 11
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==74
VrefDac_Margin_A0==23
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==24
DeviceVref_Margin_A1==40
channel==1
RxClkDly_Margin_A0==236 ps 12
TxDqDly_Margin_A0==236 ps 12
RxClkDly_Margin_A1==216 ps 11
TxDqDly_Margin_A1==236 ps 12
TrainedVREFDQ_A0==74
TrainedVREFDQ_A1==74
VrefDac_Margin_A0==24
DeviceVref_Margin_A0==40
VrefDac_Margin_A1==24
DeviceVref_Margin_A1==40
dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
soc_vref_reg_value 0x 00000015 00000016 00000017 00000015 00000014 00000014 00000016 00000015 00000016 00000014 00000014 00000013 00000015 00000014 00000016 00000016 00000013 00000013 00000015 00000014 00000012 00000015 00000016 00000017 00000017 00000015 00000014 00000016 00000014 00000012 00000012 00000015 dram_vref_reg_value 0x 00000062
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:53:31
auto size-- 65535
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-error
write-errorDDR cs0 size: 3MB
DDR cs1 size: 3MB
DMC_DDR_CTRL: 00e0002dDDR size: 0MB
DATA-W[0x00000000]:0xaaaaaaaa,R:0x677575ad
fail D0 1 2 8 9 10 11 12 14 15 16 17 18 19 20 22 23 24 26 27 30 31
DATA-W[0x00000000]:0x55555555,R:0x677575ad
fail D3 4 5 6 7 13 21 25 28 29
DATA-W[0x00000000]:0x00000001,R:0x677575ad
fail D2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000002,R:0x677575ad
fail D0 1 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000004,R:0x677575ad
fail D0 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000008,R:0x677575ad
fail D0 2 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000010,R:0x677575ad
fail D0 2 3 4 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000020,R:0x677575ad
fail D0 2 3 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000040,R:0x677575ad
fail D0 2 3 5 6 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000080,R:0x677575ad
fail D0 2 3 5 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000100,R:0x677575ad
fail D0 2 3 5 7 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000200,R:0x677575ad
fail D0 2 3 5 7 8 9 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000400,R:0x677575ad
fail D0 2 3 5 7 8 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00000800,R:0x677575ad
fail D0 2 3 5 7 8 10 11 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00001000,R:0x677575ad
fail D0 2 3 5 7 8 10 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00002000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00004000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00008000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 15 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00010000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00020000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 17 18 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00040000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00080000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 19 20 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00100000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 21 22 24 25 26 29 30
DATA-W[0x00000000]:0x00200000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 22 24 25 26 29 30
DATA-W[0x00000000]:0x00400000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 24 25 26 29 30
DATA-W[0x00000000]:0x00800000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 23 24 25 26 29 30
DATA-W[0x00000000]:0x01000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 25 26 29 30
DATA-W[0x00000000]:0x02000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 26 29 30
DATA-W[0x00000000]:0x04000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 29 30
DATA-W[0x00000000]:0x08000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 27 29 30
DATA-W[0x00000000]:0x10000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 28 29 30
DATA-W[0x00000000]:0x20000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 30
DATA-W[0x00000000]:0x40000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29
DATA-W[0x00000000]:0x80000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30 31
cs0 DataBus test failed
DATA-W[0x00300000]:0xaaaaaaaa,R:0x677575ad
fail D0 1 2 8 9 10 11 12 14 15 16 17 18 19 20 22 23 24 26 27 30 31
DATA-W[0x00300000]:0x55555555,R:0x677575ad
fail D3 4 5 6 7 13 21 25 28 29
DATA-W[0x00300000]:0x00000001,R:0x677575ad
fail D2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000002,R:0x677575ad
fail D0 1 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000004,R:0x677575ad
fail D0 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000008,R:0x677575ad
fail D0 2 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000010,R:0x677575ad
fail D0 2 3 4 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000020,R:0x677575ad
fail D0 2 3 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000040,R:0x677575ad
fail D0 2 3 5 6 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000080,R:0x677575ad
fail D0 2 3 5 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000100,R:0x677575ad
fail D0 2 3 5 7 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000200,R:0x677575ad
fail D0 2 3 5 7 8 9 10 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000400,R:0x677575ad
fail D0 2 3 5 7 8 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00000800,R:0x677575ad
fail D0 2 3 5 7 8 10 11 12 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00001000,R:0x677575ad
fail D0 2 3 5 7 8 10 13 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00002000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 14 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00004000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00008000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 15 16 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00010000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00020000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 17 18 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00040000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00080000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 19 20 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00100000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 21 22 24 25 26 29 30
DATA-W[0x00300000]:0x00200000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 22 24 25 26 29 30
DATA-W[0x00300000]:0x00400000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 24 25 26 29 30
DATA-W[0x00300000]:0x00800000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 23 24 25 26 29 30
DATA-W[0x00300000]:0x01000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 25 26 29 30
DATA-W[0x00300000]:0x02000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 26 29 30
DATA-W[0x00300000]:0x04000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 29 30
DATA-W[0x00300000]:0x08000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 27 29 30
DATA-W[0x00300000]:0x10000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 28 29 30
DATA-W[0x00300000]:0x20000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 30
DATA-W[0x00300000]:0x40000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29
DATA-W[0x00300000]:0x80000000,R:0x677575ad
fail D0 2 3 5 7 8 10 12 13 14 16 18 20 21 22 24 25 26 29 30 31
cs1 DataBus test failed
ADDR-W[0x00000004]:0xaaaaaaaa,R:0xecc7c7e3
cs0 AddrBus test failed
fail address pin cs 0 add 0x 00000004
ADDR-W[0x00300004]:0xaaaaaaaa,R:0xecc7c7e3
cs1 AddrBus test failed
fail address pin cs 1 add 0x 00300004 ra5 ra6
100bdlr_step_size ps== 123
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
response= 43610
get rpmb counter error 0xffffffff
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000K▒▒▒▒▒ 0
FIP H▒R▒
▒▒▒▒R+▒▒ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
itch 1 o,
▒z▒5
fastboot data verify
verify result▒&SSHh▒▒▒max: 2, cur: 1. Boa▒d id: 255. Force l▒ cfg
LPDDR4 probe
ddr clo to 792MHz
Load▒ddrfw fr▒
▒ src: 0x0003c200, des: 0x@ffd0000, si~e▒ 0x0000c000, p▒▒ 0
0000000▒Y[[,▒ݥэ▒▒0 ok
)INFO : End of initialization
KNFO : TraiC