I’m looking at the Radxa Orion O6N board, which uses the CIX P1 (CD8160) SoC.
I understand the board exposes two M.2 M-Key connectors with PCIe Gen4 x4 lanes.
I’m interested in exploring the possibilities of interconnection on this board, not just in terms of PCIe Endpoint mode, but considering the full range of options including Root Complex, peer-to-peer PCIe, NTB (Non-Transparent Bridge), or even CCIX/CXL links.
My goal is to understand whether the hardware and software could allow high-bandwidth communication between multiple boards or SoCs, potentially for clustering, memory sharing, or distributed computing tasks.
I really appreciate the direction and hardware offering from Radxa, even though I’m not yet sure how relevant it will be for my specific use case.
Thanks for the reply, it helped clarify several parts of the PCIe architecture.
I’m running into a bit of uncertainty regarding the PCIe layout of the O6N.
The CIX P1 SoC provides several PCIe controllers, and one of them can operate either as a Root Complex or an Endpoint.
In theory, this opens the door to building PCIe topologies with multiple independent links and different roles on each link.
However, looking at the O6N board, it’s not obvious how these controllers are actually routed.
The two M.2 M-Key slots each expose a PCIe Gen4 x4 interface, but it’s unclear whether these come from two separate PCIe controllers on the SoC or from a single x8 controller split into two ×4 links.
That’s the part I’m struggling with, if each M.2 slot is driven by its own controller, then certain PCIe configurations are feasible, but if both slots are derived from one bifurcated controller, then both ports share the same PCIe block and some configurations simply aren’t possible, even if the SoC itself could theoretically support them.
So I’m just trying to understand the actual PCIe mapping on the O6N to know what is genuinely achievable on this hardware.
Thank you for sharing your knowledge. However, I am still expecting clarification on this point.
