Orion O6 Debug Party Invitation

hrw · February 12, 2025, 10:29am

Also logs from running BSA ACS in EFI shell?

BSA ACS ACPI
BSA ACS DT (I never used this one)

Run as Bsa.efi and also as Bsa.efi -v 1 for verbose output. Board will require hardware reboot after each run.

RadxaNaoki · February 12, 2025, 11:36am

Is CONFIG_ACPI_CPPC_CPUFREQ enabled?

Try earlycon=pl011,mmio32,0x40d0000 for serial console(UART2).
EDIT: loglevel=0 ?

willy · February 12, 2025, 1:29pm

Hi Naoki!

Yes, but it’s in module:

$ grep CPPC .config
CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ACPI_CPPC_CPUFREQ_FIE=y
CONFIG_ACPI_CPPC_LIB=y

I had tried to load it and it reported “no such device” ot something like this, so I didn’t insist. But I could rebuild the kernel with it set to “y” just in case it matters. I remember keeping it as a module for the Altra board that is a bit capricious and occasionally switches to 1 GHz until either a reboot or a reload of the module

OK will try that, thank you! I suspected something around this without knowing what to enter, even though I did see that the UART was indeed pl011.

Regarding loglevel=0, I was about to say “no I don’t have this” but looking at the cmdline, I’m indeed seeing it on my alt kernel now! I don’t know how I managed to get that one by hacking on the grub.cfg but it certainly does not help Ah it comes from my attempt to boot the fedora kernel, where it’s present. I’ll drop it. Good catch, thank you!

willy · February 12, 2025, 9:00pm

@RadxaNaoki I can confirm that the console is now OK, but CPPC… still nothing, even once hard and updated to 6.12.13. There isn’t even a message about it during boot, so I suspect it’s not enumerated in the ACPI tables. I looked a bit for it but I’m not familiar with ACPI tables so I’m not sure what to look for.

RadxaNaoki · February 13, 2025, 1:11am

Please try vanilla defconfig.

$ uname -a
Linux orion-o6 6.12.13 #1 SMP PREEMPT Thu Feb 13 00:53:55 UTC 2025 aarch64 aarch64 aarch64 GNU/Linux
$ lsmod | grep cppc
cppc_cpufreq           12288  0
$ ls /sys/devices/system/cpu/cpu0/acpi_cppc/
feedback_ctrs    lowest_freq            nominal_freq    wraparound_time
guaranteed_perf  lowest_nonlinear_perf  nominal_perf
highest_perf     lowest_perf            reference_perf
$ cat /sys/devices/system/cpu/cpufreq/policy0/scaling_{min,max}_freq
800000
2500000

Please check /sys/firmware/acpi/tables/SSDT2.

night · February 13, 2025, 2:07am

It seems that Windows 24H2 has some issues in supporting different PE architectures. You can try disabling all the little cores (core 0-3) to see if it works.

willy · February 13, 2025, 5:26am

SSDT2 is properly there. I’ll then try defconfig, thank you for the test!

OK now I can confirm that cppc_cpufreq in defconfig works properly, that’s perfect, thanks! I’ll diff the configs to figure what makes the difference, but for now it looks like mainline is working fine for me.

Bryan_F · February 14, 2025, 4:32am

Here’s from Debian (Linux debian 6.12.9+bpo-arm64 #1 SMP Debian 6.12.9-1~bpo12+1 (2025-01-19) aarch64 GNU/Linux)

Can’t get bsa.efi to log to file. I run Bsa.efi -v 1 -f bsa.out, a bunch of tests look to pass and then the screen goes corrupt, but nothing in the file on reboot. I’ll try again at some point

hrw · February 14, 2025, 9:20am

For BSA ACS it is better to connect serial console and log it’s output rather than trying to log into file.

ACS leaves system in a state where reboot is required.

hrw · February 14, 2025, 6:27pm

I got BSA ACS (ACPI mode) results from one of board owners.

Looks quite nice, some issues present, part of them can be solved by firmware.

GTDT needs EL2 Virt Timer (someone used arm v8.0 firmware as base)
SPCR should be added as it is mandatory table
there are no system timers in tables
also no PE always-on timers

I suspect that whoever did firmware did not looked at BSA ACS or FWTS results.

willy · February 15, 2025, 6:57pm

Just FYI, I could bisect my configs this afternoon and finally found the option that is required for CPPC to work. The config requires CONFIG_ARM64_AMU_EXTN=y. It was disabled in my generic config, as the help text says that using it on non-compliant firmware can result in hangs at boot. Now CPPC seems OK on mainline with my portable config. I’ll retest later if kernels having this option still boot fine on RK3588. We’re getting close to something quite clean now.

jack · February 21, 2025, 4:26am

Upstreaming starts:

https://patchwork.kernel.org/project/linux-arm-kernel/patch/20250220084020.628704-2-peter.chen@cixtech.com/

willy · February 21, 2025, 7:12am

yep, I noticed it yesterday

dominik · February 21, 2025, 9:18am

Great news
I have question regarding pcie slot, it was said that no bifurcation support at this time, is that hardware limitation or just no plans on software for that now?

jack · February 21, 2025, 9:25am

Hardware limitation

DualTachyon · February 21, 2025, 9:52am

Is JTAG/SWD available on easy-access pin/header and is it unlocked/unlockable on the SoC? (Secure boot seems present, if so this might disable it).

Vladimir_Smirnov · February 24, 2025, 12:13pm

That is a good thing, but that should be done in parallel with publishing source code for the current kernel.

jack · February 24, 2025, 12:56pm

It’s already on the schedule, next week we will publish the 6.1 kernel source code, EDK2 source code and the Debian image build scripts.

neggles · February 25, 2025, 4:29am

no source for the vendor 6.6 (ACPI) kernel?

chalkin · February 26, 2025, 3:01am

The UEFI GOP of the o6 does not work on some high-resolution, high-refresh-rate monitors (e.g., my display defaults to 2880×1800 @90Hz), resulting in a black screen, but it functions properly at 1080p resolution on my Rock5B UEFI.

NOTICE:  BL2: v2.7(debug):Beta_2.0.3_release
NOTICE:  BL2: Built : 20:04:34, Jan 15 2025
CRYPTO_LITE  TOP_STAT_CFG0_STAT:0x70018c63
CRYPTO_LITE  Wait SW initialization done!
CRYPTO_LITE  Software initialization done!
CRYPTO_LITE  Current host ID: 1
CRYPTO_LITE      RN_POOL is: Secure
CRYPTO_LITE      ACA is: Secure
CRYPTO_LITE      HASH is: Secure
CRYPTO_LITE      SCA is: Secure
CRYPTO_LITE      ACA SRAM size:          8192 Bytes
CRYPTO_LITE      ACA CQ depth:           8
CRYPTO_LITE      HASH CQ depth:          8
CRYPTO_LITE      SCA CQ depth:           8
CRYPTO_LITE      HASH long ctx number:   4
CRYPTO_LITE      HASH short ctx number:  4
CRYPTO_LITE      SCA long ctx number:   4
CRYPTO_LITE      SCA short ctx number:  4
CRYPTO_LITE      OTP device initial value:  1
CRYPTO_LITE      OTP shadow registers save to AO
CRYPTO_LITE      OTP device: NOT exist
CRYPTO_LITE      TRNG internal source: Exist
CRYPTO_LITE  CE Version: EAC REL r3p1
INFO:    Using crypto library 'CIX SEC'
INFO:    BL2: Doing platform setup
INFO:    Configuring TrustZone Controller
INFO:    Total 2 regions set.
INFO:    Configuring TrustZone Controller
INFO:    Total 2 regions set.
INFO:    Configuring TrustZone Controller
INFO:    Total 2 regions set.
INFO:    Configuring TrustZone Controller
INFO:    Total 2 regions set.
INFO:    BL2: Loading image id 3
INFO:    Loading image id=7 at address 0x80200000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=7 loaded: 0x80200000 - 0x80200650
INFO:    SE lc: 7, sec: 1, img_id: 7
INFO:    copy ROTPK from DDR
INFO:    copy done
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    md_alg: 6
INFO:    hash_len: 32
INFO:    Loading image id=9 at address 0x80200000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=9 loaded: 0x80200000 - 0x8020065a
INFO:    SE lc: 7, sec: 1, img_id: 9
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    Loading image id=13 at address 0x80200000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=13 loaded: 0x80200000 - 0x80200530
INFO:    SE lc: 7, sec: 1, img_id: 13
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    Loading image id=3 at address 0x80200000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=3 loaded: 0x80200000 - 0x8021961d
INFO:    SE lc: 7, sec: 1, img_id: 3
INFO:    BL2: Loading image id 4
INFO:    Loading image id=10 at address 0x80500000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=10 loaded: 0x80500000 - 0x80500668
INFO:    SE lc: 7, sec: 1, img_id: 10
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    Loading image id=14 at address 0x80500000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=14 loaded: 0x80500000 - 0x805005ce
INFO:    SE lc: 7, sec: 1, img_id: 14
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    Loading image id=4 at address 0x80500000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=4 loaded: 0x80500000 - 0x805cd8d8
INFO:    SE lc: 7, sec: 1, img_id: 4
INFO:    BL2: Loading image id 5
INFO:    Loading image id=36 at address 0x84400000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=36 loaded: 0x84400000 - 0x8440063a
INFO:    SE lc: 7, sec: 1, img_id: 36
INFO:    copy ROTPK from DDR
INFO:    copy done
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    md_alg: 6
INFO:    hash_len: 32
INFO:    Loading image id=11 at address 0x84400000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=11 loaded: 0x84400000 - 0x8440066b
INFO:    SE lc: 7, sec: 1, img_id: 11
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    Loading image id=15 at address 0x84400000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=15 loaded: 0x84400000 - 0x84400541
INFO:    SE lc: 7, sec: 1, img_id: 15
INFO:    rsa len: 384
padding_type:3
rsa bits:5
CRYPTO_LITE  RSA verify pass, pkcs2v1
INFO:    Loading image id=5 at address 0x84400000
INFO:    pb.tfabde:0
INFO:    Flash load BL3X!
INFO:    Image id=5 loaded: 0x84400000 - 0x84600000
INFO:    SE lc: 7, sec: 1, img_id: 5
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0x80200000
INFO:    SPSR = 0x3cd
INFO:    Start sky1 scmi server!
NOTICE:  BL31: v2.7(debug):Beta_2.0.3_release
NOTICE:  BL31: Built : 20:04:34, Jan 15 2025
INFO:    boot_core_index 10 
INFO:    cpu mask 0xa000
INFO:    GICv4 without legacy support detected.
INFO:    ARM GICv4 driver initialized in EL3
INFO:    Maximum SPI INTID supported: 543
INFO:    drv_mbox_init
INFO:    Send CMD: ECHO Request
NOTICE:  Send CMD: 0x82000001
INFO:    Got Echo RSP, Mbox channel is ready...
INFO:    plat_cix_scmi_setup
INFO:    SCMI driver initialized
INFO:    ###########ni700-qos setting###########################
INFO:    [MMHUB_CSI_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_CSI_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_CSI_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_CSI_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU0_AFBC_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU0_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU0_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU1_AFBC_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU1_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU1_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU2_AFBC_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU2_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU2_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU3_AFBC_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU3_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU3_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU4_AFBC_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU4_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_DPU4_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_ISP_AFBC_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_ISP_SLV0]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_ISP_SLV1]:override--1 read_qos--0f write_qos--0f 
INFO:    [MMHUB_NPU_SLV0]:override--1 read_qos--0d write_qos--0d 
INFO:    [MMHUB_NPU_SLV1]:override--1 read_qos--0d write_qos--0d 
INFO:    [MMHUB_VPU_SLV0]:override--1 read_qos--0d write_qos--0d 
INFO:    [MMHUB_VPU_SLV1]:override--1 read_qos--0d write_qos--0d 
INFO:    [SYSHUB_AUIDO_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [SYSHUB_USB2_0_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USB2_1_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USB2_2_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USB2_3_SLV]:override--1 read_qos--0f write_qos--0f 
INFO:    [SYSHUB_USB3_0_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USB3_1_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USBC_0_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USBC_1_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USBC_2_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    [SYSHUB_USBC_DRD_SLV]:override--1 read_qos--08 write_qos--08 
INFO:    ######################################################
INFO:    ###########ci700-qos setting###########################
INFO:    [CI700_RNF0]:override--1 read_qos--0d write_qos--0d 
INFO:    [CI700_RNF1]:override--1 read_qos--0d write_qos--0d 
INFO:    [CI700_RNF2]:override--1 read_qos--0d write_qos--0d 
INFO:    [CI700_RNF3]:override--1 read_qos--0d write_qos--0d 
INFO:    [CI700_GPU_RNI64_S0]:override[r-w]--[1-1] read_qos--0b write_qos--0b 
INFO:    [CI700_GPU_RNI64_S1]:override[r-w]--[1-1] read_qos--0b write_qos--0b 
INFO:    [CI700_GPU_RNI72_S0]:override[r-w]--[1-1] read_qos--0b write_qos--0b 
INFO:    [CI700_GPU_RNI72_S1]:override[r-w]--[1-1] read_qos--0b write_qos--0b 
INFO:    [CI700_PCIE]:override[r-w]--[1-1] read_qos--08 write_qos--08 
INFO:    [CI700_SYSHUB_SMMU]:override[r-w]--[1-1] read_qos--0f write_qos--0f 
INFO:    [CI700_DFD_TMC]:override[r-w]--[1-1] read_qos--0f write_qos--0f 
INFO:    [CI700_MMHUB_SMMU]:override[r-w]--[1-1] read_qos--0f write_qos--0f 
INFO:    [CI700_PCIEHUB_SMMU]:override[r-w]--[1-1] read_qos--0f write_qos--0f 
INFO:    ######################################################
INFO:    cix_qspi_init start...
INFO:    cix_qspi_init end...
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
INFO:    last reboot reason:0x10 
INFO:    BL31: cortex_hunter: CPU workaround for cve_2022_23960 was applied
INFO:    SDEI platform setup
INFO:    BL31: Initializing BL32
E/TC:10    console_init:108 Cix uart register successful
E/TC:10    console_init:108 Cix uart register successful
I/TC: 
I/TC: OP-TEE version: Beta_2.0.3_release #1 Wed, 15 Jan 2025 20:08:15 +0800 aarch64
I/TC: OP-TEE cix version: Beta_2.0.3_release-3.17-0af95526e956
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
MBEDTLS_CORE  host[1] waits sw_init_done...MBEDTLS_CORE  [DONE]
MBEDTLS_CORE   HASH driver init success!
MBEDTLS_CORE   SCA driver init success!
MBEDTLS_CORE  SRAM Pool Base: 0x80000000, size: 0x2000, alignment: 0x10
MBEDTLS_CORE   ACA driver init success!
E/TC:10 00 tee_otp_get_hw_unique_key:123 Get hw key:
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x84400000
INFO:    SPSR = 0x3c9
[65.387] [UEFI] E3C1 XspiInitDxeStart
[65.388] [UEFI] E400 XspiInitDxeEnd
[65.476] [UEFI] E2C1 PcieInitDxeStart

Root Port 0 Link up fail

Root Port 1 Link up fail

Root Port 2 Link up fail
[65.850] [UEFI] E300 PcieInitDxeEnd
One display device is found on typec port1!
Update Platform Config Param GopDisplayPort=0x1
total 6 modes (current pixel clock 50671, width 2880, height 1800)