We were so excited to announce the Radxa Orion O6 motherboard on the CIX Ecosystem Event in Shanghai on 18th, Dec. With CIX’s generous donation of the CD8180 chips, we are so glad to invite the Radxa developers to join the Orion O6 debug party.
a USB SPI flash programmer, O6 has a repealable SPI flash header
multiple USB to TTL to access the multiple UARTs on the motherboard
a NVMe SSD for OS installation
familiar with UEFI shell, Linux OS booting etc
The O6 debug party samples package comes with the follow items:
an O6 motherboard with 16GB LPDDR5
a heatsink with fan
an Acrylic shell for motherboard protection
a spare SPI flash chip for bios backup
an Orion O6 sticker
The packages are expected to be shipped before 20th, Jan.
Radxa team will contact the developers based on our previous experience one by one privately by email or forum PM or on discord. If you are a developer and interested in Orion O6 and was missed by us in the following week, you can post under this thread and explain why you should receive one O6 to develop/hack with.
For other questions about the Orion O6 or the CIX team/company, you can post under this thread, we will reply as much as we can. Some questions will also be sent to CIX for their answers.
Or maybe just the need to recover a failed upgrade (or more precisely a successful upgrade of an incorrectly configured boot loader, quite common actually). Usually this is worked around by booting from the micro-SD but possibly here it’s different, maybe the SoC only boots from SPI (like a PC in fact).
We can upgrade the BIOS from UEFI shell or with USB fastboot command. But if you develop the UEFI/BIOS, you need to flash the BIOS often and may break it. Then you need to pull out the SPI flash and program with an external programmer.
I’ve used quite a lot both the BusPirate v3.6 (very slow but it’s a good starter), and the now ubiquitous “CH341A programmer” that you can find in millions of instances on Aliexpress. One of them is commonly sold with the DIL-do-SOP8 adapter and it’s really convenient to use. I do recommend that last one (simple and fast). The only thing is to be careful about the orientation between SPI and I2C chips because it can sometimes be confusing, but till now I’ve only heated chips, never fried them
Also regarding the UART, I’ve long had good experiences with the CH340 variants (I particularly like the tiny CH340E, we’re finding many cheap 1cm² boards with it that you can buy in packs of 10pcs). They support all common speeds including 1.5 and 2 Mbauds and even ESP8266’'s 76800.
Maybe can use https://www.flashrom.org/, directly through a Linux generic spi interface device(linux even has drivers for emulating gpio as a spi device) on another SBC
@hipboi is the debug party revision the final revision that you guys know of or is it one with a known HW bug but that’s not so critical that the board can still be used for debug?
You said that UEFI+ACPI will come at some point in future as you went UEFI+DT for now.
I hope that dump of ACPI tables and results of BSA/SBSA/PC-BSA ACS will be available when UEFI+ACPI code drop happen.
Used ACS tests during work on SBSA Reference Platform in QEMU/EDK2/TF-A and those help catching hardware/firmware issues. Some hw ones cannot be easily fixed, some can be hidden by firmware.
Planning to buy 64GB one if reviews convince me to spend money on a board.
Picking up the suggestion here I want to ask about CD8180’s PCIe ‘bifurcation’ capabilities.
As I may have understood correctly it’s not only about the SoC’s possibilities how to ‘spread’ PCIe lanes but also board layout (with RK3588 the four Gen3 lanes could be used in a 4 x x1 config but the clocks must also be considered and as such with Rock 5B only a 2 x x2 config for the M.2 slot is possible, right?)
So speaking about the PCIe x8 and the M.2 x4 slot: is it possible to use them in other configs, e.g. the PCIe slot in a 4 x x2 and the M.2 slot in a 4 x x1 or 2 x x2 setup?
Beta 1 image release will be UEFI + DT and it will be available on 15th, Jan and Beta 2 image release will be UEFI + ACPI, the timeline is expected before Feb.
I hope that dump of ACPI tables and results of BSA/SBSA/PC-BSA ACS will be available when UEFI+ACPI code drop happen.
The EDK2 source code will be available, so you can just edit it.
