Thank you Naoki. I’m very pleased to see that it looks pretty good out of the box, with measured CPU frequencies matching the advertised OPP, and excellent RAM timings for tests from the A720 cores! The CPU cores ordering is very strange however, I don’t know if it’s caused by the cores declaration in the DTB or any such thing:
CPU cluster policy speed speed core type
0 0 0 800 2500 Cortex-A720 / r0p1
1 0 1 800 1800 Cortex-A520 / r0p1
2 0 1 800 1800 Cortex-A520 / r0p1
3 0 1 800 1800 Cortex-A520 / r0p1
4 0 1 800 1800 Cortex-A520 / r0p1
5 0 5 800 2300 Cortex-A720 / r0p1
6 0 5 800 2300 Cortex-A720 / r0p1
7 0 7 800 2200 Cortex-A720 / r0p1
8 0 7 800 2200 Cortex-A720 / r0p1
9 0 9 800 2400 Cortex-A720 / r0p1
10 0 9 800 2400 Cortex-A720 / r0p1
11 0 9 800 2400 Cortex-A720 / r0p1
=> 1 2.5G big core, 4 1.8G small cores, 2 big 2.3G cores, 2 big 2.2G cores, 3 big 2.4G cores. That’s 5 different clusters, compared to the expected 3 clusters which should be each made of 4 identical cores.
Regardless, despite the many different frequencies, these frequencies are reasonably good already (which explains the performance gains you measured on the kernel build).
In fact, I suspect that for the little cores (A520), where the DRAM timings are particularly bad, that’s exactly the same issue as on the rock5 where the DMC doesn’t leave powersave mode when only little cores are running, and very likely that the timings will be better if you change the DMC to performance mode. But for tests involving all cores at once, it should not change anything, since the big cores will turn the DMC to high performance mode anyway. On the rock5, running this significantly improves the little cores performance for me:
echo performance > /sys/devices/platform/dmc/devfreq/dmc/governor
I suspect you’ll see the same here. But again it will only affect workloads running exclusively on small cores, so nothing very important for your general tests.