JTAG/SWD debugging?


the RK3308 manual describes the availability of JTAG/SWD (see p. 38 - pins JTAG_TCK/JTAG_TMS seem to implement clock and data for SWD).

It seems that the two pins are multiplexed with SPI2_MISO and SPI2_MOSI (GPIO55/54), which are available on pins 19 and 21 of GPIO header 1.

I haven’t tried using the SWD interface so far (just received the board two hours ago). Has anyone tried to use SWD with e.g. OpenOCD already? If so, does one have to configure something (register, pin config at powerup) in order to access SWD?

Any hints are appreciated…

– Michael

I am not sure if OpenOCD can work with A35 core. Here is a diagram for you to refer. You need pull up for the SWD pins.

i got some touch with openocd and swd see here and here

i have $6 jlink probe hooked to tms/tck swd pins

openocd change for rk3308

without sd card bootrom waits on usb for rkdeveoptool to upload bootcode to sram.


  • halt cores
  • resume cores


  • work-area (sram)


  • sw reset (using watchdog or clock reset unit).
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Very nice. Maybe a little bit more how to for the community member who wants to dive into the bare metal development? :wink:

header1 pins:
#17 <-> VREF/3V3
#25 <-> GND

do not insert sd card, uboot pinctrl sets grf which disables swd on those pins and enables on them uart pins.

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after compilation of uboot i tried to load it to memory without success (~4.8mb).
using rkdeveloptool db rk3308_loader_uart0_m0_emmc_port_support_sd_20190717.bin before loading using gdb leads to, at least, successfull load.
maybe upstream evb-rk3308_defconfig is not the best choice.

nice to have / todo:

  • tcl script for loading binary for ddr config
  • script which will do same instead

to play with uboot, quick and dirty way is:
mw.l 0xff000034 0x0ff00440

revisited ii:
with this we can go better :slight_smile:

revisited iii:
seems all cortex-a35 chips from rockchip (rk1808, px30, rk3308, rk3326) have jtag pins enabled, rk3308.cfg merged to master of openocd, will be in 0.11.0

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