I do use KVM on my Ubuntu 20 Linux desktop running a Ryzen 9 5950 with 64GB RAM, and I’ve even managed to set up an Arm (aarch64) VM via Qemu as well, but a) It was VERY difficult to get working and b) It feels slow.
It also wouldn’t be my first Arm SBC. I have a RPi 3B+ running Raspbian. It’s a DNS for my local LAN and it drives my old Epson flatbed scanner, which no longer has Windows support.
There is no ‘8nm process’ since these numbers today are just marketing BS. At least according to TSMC’s vice president of corporate research (TSMC is the foundry having the most advanced process nodes today so maybe he knows a little bit what he’s talking about):
Yeah, but I was talking about running an arm64 Linux distribution in a VM on one of these cores which is really easy and super fast since both cores and OS support virtualization. But running macOS isn’t everybody’s 1st choice so nevermind 
Oh, on an M1/M2 Mac? Yeah, since I don’t already own one, it would be a really expensive way to go.
are they though?
so then what happen when and if they get to 2 or even 1nm process?
you know there is a thing called quantum tunneling , are you saying that is not real either?
or are you saying that they are just hyping and that they are not really using the processes they are claiming?
from my understanding they are getting dangerously close to Moore’s law hitting the wall , and that they can only go to 3 or 2 nm before quantum tunneling become an issue,
then the only thing to do is use layering techniques to increase performance
They are not because of quantum tunnelling because we are at such small quantum size the electrons pass through without registering.
When they say 8nm they are the smallest lithographic process avail will be 8nm but much will be bigger process so really its not, but capable of 8nm or less if it wasn’t for quantum tunnelling where there is so little stuff there the electron just passes straight through.
Its all stuff we don’t need to know for use and far too complex but we are already past much of what can be done with conventual silicon and where they can mitigate some of it is at that process spec but more and more isn’t.
I was reading about it a month ago and about special gate keeper circuits to help mitigate quantum tunnelling and as per usual have forgot most of what I read.
Who cares what I’m saying? Or all the tech journalists babbling about ‘nm process nodes’? What about listening to those who should really know?
Here we go again:
But hey, that’s just TSMC’s vice president of corporate research! I guess we should better trust marketing departments, tech magazines, bloggers and the whole of YouTube telling us about ‘nm processes’ when they in reality just report about a fab’s node name that has some specific number in its name that gets lower and lower every year which poses the problem which numbers the marketing departments will choose in a few years since they’re obviously getting close to 1 with their node names within the next time.
There is a good bit on wikipedia about 7nm node
Since 2009, however, “node” has become a commercial name for marketing purposes[6] that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[7][8][9] TSMC and Samsung’s 10 nm (10 LPE) processes are somewhere between Intel’s 14 nm and 10 nm processes in transistor density.
But yeah its a trade name for
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology.
There is practically one firm who has a near monopoly on the lithographic machines that do the etching.
I think its them who conjure up new node process names.
That monopoly might also cause a new silicon shortage as apparently the US has banned them from supplying new node technology and existing to China as TSMC is based in Taiwan
If you look at the new 3nm process https://en.wikipedia.org/wiki/3_nm_process#3_nm_process_nodes
The Transistor gate pitch (nm) really is >= 40nm
Its sort of approx effective density in die size and efficiency and could be wrong about AMSL but it always seems to be co-ordinated even though the transistor technology might be different so always presumed it was.
Nope reading its https://en.wikipedia.org/wiki/International_Roadmap_for_Devices_and_Systems which is https://en.wikipedia.org/wiki/International_Technology_Roadmap_for_Semiconductors now minus China
Please read the stuff you’re referencing. It begins with “…the ITRS defines the 7 nm process as…” – if you click on the ITRS link you can read “As of 2017, ITRS is no longer being updated”. 2017!
Now the third and last time: your ’ 7 nm process’ article talks about TSMC’s N7 process. Now what TSMC itself (not the marketing department but those who actually do the work) have to say: ‘while we might like to think that the N7, N5, and N3 names it’s using for its 7nm, 5nm, and 3nm nodes relate to the gate length of transistors, they’re effectively just brand names.’
Who should we trust now? Some ‘enthusiasts’ writing stuff on Wikipedia (that gets copy&pasted by ‘tech journalists’, bloggers, Youtubers and so on) or the one who really knows?
Asides that Wikipedia in most areas is full of BS and this especially applies to semiconductor manufacturing where fanboys of AMD, Intel, Apple and whatever else do edit articles.
If TSMC for example presents a new process called N3 and a slide tells ‘up to 1.7 more density than N5’ then within no time some wiki clown will create out of this ‘up to’ marketing claim a static 1.7 multiplicator and multiplies some chip density BS number from the past with this new static factor and from then on Wikipedia claims ‘N5: 185 MTr/mm2’ but ‘N3: 314.73 MTr/mm2’ which is plain BS or just failed math combined with wrong assumptions and missing due diligence.
And everyone familiar with this technology knows this since different chip areas have different densities, for example ‘SRAM density is disclosed at only getting a 20% improvement’. Now compare this with Wikipedia where some copy&paste clown failing with math multiplied some also just vaguely estimated BS number for the N5 process with 1.7 to generate a new BS number for N3.
And always remember what TSMC’s VP of corporate research had to say at his Hot Chips keynote about these N3, N5 and N7 names: ‘they’re effectively just brand names’:
BTW: to stop all this useless nitpicking…
When Rockchip announced RK3588 they we’re talking about an ‘8 nm process’.
So let’s look at Wikipedia first since we all need to believe there lives the truth: https://en.wikipedia.org/wiki/8_nm_process
What does this really tell us? It’s made by Samsung since TSMC has no process with 8 in its name and GlobalFoundry’s process name numbers do not go below 12.
So we’re talking about a so called ‘extension’ of Samsung’s 10LPP process (as such the marketing department decided that it would be a great idea to decrement the 10 number simply by 2 to have a nice name with an 8 inside: 8LPP) which is said to have a fin pitch of 42nm and a gate pitch of 64nm:
Considering that this is supposed to be a thread created for general discussion about a specific device, there is currently way too much discussion about wholly irrelevant things.
Now that the board is in the hands of some, I would have thought that more focussed discussion would be of far greater use to those who have been waiting for this to come along.
There is even a dedicated thread for those invited to the debug party to discuss the more technical areas that may perhaps be of less use to end users and more for the Radxa devs.
As part of the general use that these boards will get, I am surprised that we have not seen them sent out to the usual YT reviewers that will cover video, gaming and things that are likely to be of greater interest to the masses.
In addition, as well as debug testing and the like, Radxa should consider sending some out to average users to put through it’s paces and receive more basic and generic feedback from those that are likely to be the key consumer purchasers (those who have likely bought the P4 and are looking for the next thing to upgrade to).
Key prospective marketing opportunities are being missed by Radxa.
We already have some idea of what the RK3588 boards can potentially achieve from video posts from users of competing products and although the Rock 5 is behind the curve, its prospective price could be compelling enough for people to hold on to their cash for a while longer.
But the longer the wait, without some real world, more mass use demonstration can lead to money being spent elsewhere.
Have a dual party invite. One for the high level techies and one for the average users who are going to be the ones to gush over the product and more likely promote its potential purchase.
These are Dev boards pre-release engineering samples with testers doing what testers do.
It would be a big mistake to release to the usual YTer’s until the testers and fixes and final production version is released.
It was just a small batch that Radxa forward to certain knowns who will test with various configs that might not be considered your average user.
Open testing of opensource hardware in an open conversation is just a positive as shut doors often blind to oversights.
I had read this a few weeks ago, I think it sums up the situation well.
Actually, why do we bother with the “intrinsics” of the process nodes? It is far more complicated than what we could read in Wiki, as most of the details are trade secret for sure, especially the cutting edge ones. I remember that back in the days (like in late 90s and early 00s) when the process nodes naming really means something, they were something like 130nm and 90nm. After that, the transistor “form” changed, say from “traditional” MOSFET to FINFET to GAA nowadays. The naming then no longer really referring to the transistor size, and if we read “carefully” the foundries would say “7nm class process” instead of “7nm process”. In addition, we also have the substrate to consider, like SOI (lower leakage) and GaAs (higher switching frequency) that would also affects transistor characteristics. And lately we also have GaN that’s used in power supples (I have a few PD ones already), which should have good “heat parameters”. There is no “single” parameter that would dominate the performance of a design. Oh, and let’s not talk about the differences between analog and digital circuit…
I really hate my BJT classes back in college 
We shouldn’t as usage stats and benchmarks give us end stats.
But yeah even the shape as the nodes is not representative of gate length and such which are all 2d measurements whilst a lot of innovation is with 3d shape such as troughs or fins as in FinFet.
We have this strangely prearranged ITRS roadmap that you can expect the next gen to be more efficient or powerful.
Sorry if I may have missed this but we are in Q3, can the Rock 5B be ordered and redeem the $50 coupon? I got mine from allnet but it doesn’t seen to be in stock there.
In June, didn’t you already pay attention to this product?
They didn’t give any firm dates
expected Q2, 2022
Currently @ revision v1.4 and guess it will be as long as it takes.
July is soon first month of Q3, and ending !
Is there some videos showing real testing on these boards, showing real Debian in duty ?