I think a lot of the confusion around the idle power numbers comes from a mismatch between the hardware design and how power state is currently understood.
The CIX P1 isn’t just a classic “CPU + RAM + IO” SoC anymore. It’s a highly integrated set of memory masters (CPU, GPU, NPU, PCIe, Ethernet, DMA, etc.) that all share the same memory and interconnect fabric.
In that setup, the SMMU, the NoC and the DDR controller are really at the center, and they largely determine whether the system can go into deep idle or not.
From Linux’s point of view, things can look completely idle, and that’s a valid view. CPU flame graphs clearly show cores spending most of their time in cpuidle.
But that only tells us what the CPUs are doing. It doesn’t say much about what’s happening in the interconnect, the SMMU, or the DDR side.
With this kind of architecture, idle isn’t a per-device thing anymore, it’s global.
If even one piece of the system is still considered active, a DMA path that isn’t fully shut down, an SMMU context that’s still there, an interrupt source, or a NoC that can’t be sure there’s no traffic, the memory subsystem stays up.
When that happens, DDR can’t really go into deep self-refresh, and power doesn’t drop much.
In the end, the PMU is the one that makes the call. No matter what Linux reports, it’s the PMU, following firmware policies, that decides whether clocks and power rails can actually be turned off.
If it’s not confident that everything is quiet, it will stay conservative and keep things powered.
That’s also why comparing this directly with older platforms is tricky. Older SoCs generally fit Linux’s power model better: simpler interconnects, fewer global dependencies, and clearer idle paths.
With the P1, the hardware has clearly moved toward a more system-level power model, and the software stack as a whole firmware, PMU setup, kernel abstractions is still adjusting to that.
So this doesn’t really look like a single bug or a broken SoC.
It looks more like a very integrated design exposing the limits of how power management is currently handled across hardware, firmware and the OS.