GPIO voltage & short circuit to GND

Unfortunately the RK3399 supports only 1.8V and 3.0V I/O. Most of the GPIOs on the GPIO header are 3.0V as stated in the Wiki. I’ve read the RK3399 TRM, Data sheet, and Design Guide but I have not found any information on how robust the GPIO drivers are.

As stated in this wiki page some pins have pull ups to 3.3V. However, the maximum voltage is 3.15V according to the RK3399 data sheet. Why did you choose to pull the pins up to 3V3 instead of 3V0? The internal body diodes will clamp the voltage to ~3V15 anyway. A pull up to 3V0 would at least be within specification. Or do you have any indication from Rockchip that pull-up resistors to 3V3 are ok?

If over-voltage on those pins is ok, how much current is allowed to flow? With 4k7 to 3V3 I would estimate somewhere between 64 to 32 µA (depending on whether you take the difference to 3V15 or 3V0).

The spi-install wiki page even suggests shorting the SPICLK GPIO to GND.

The Design Guide states that in boot mode the SPI GPIOs are configured for 7mA drive strength. None of the documents state that a continuous short to GND is ok. Do you have any more information on this?

If there is ever a 1.5 revision of the Rock Pi I would suggest putting 3.0V on the 3.3V GPIO header pins 1 and 17. I’d also change the pull-ups for I2C to the 3V0 rail (or maybe require external pull-ups?). Any 2.7 - 3.6V-device powered from the GPIO pins 1 and 17 will work with 3.0V and it will have the correct voltage on the GPIOs.

As it is you either require:
(1) external 3.0V power supply
(2) series resistors on the GPIO lines to at least limit the current into the GPIO pins of the RK3399
(3) level shifter IC on the GPIO
(4) risk damaging the GPIO pins - or even the whole chip by applying 3V3 without protection

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I think that the wiki page you refer to may be somewhat out of date, or simply in error. In particular, look at page 12 of the rev. 1.3 schematic at the top center of the page, it is showing that GPIO2_A0, GPIO2_A1, I2C7_SDA, I2C7_SCL, GPIO2_B1, and GPIO2_B2 are pulled up to VCC_3V0 via 4.7k. Those 6 pins correspond to the line in the wiki about being pulled up to 3v3.

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And probably the reason why they are supplying 3v3 on pins 1 and 17 have to do with current. VCC_3V0 is output from the PMIC and maximum of 300 mA. VCC3V3_SYS is supplied by a 2A buck.

Although I do agree that it would be better to have 3.0 on the header.

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The Design Guide states that in boot mode the SPI GPIOs are configured for 7mA drive strength. None of the documents state that a continuous short to GND is ok. Do you have any more information on this?

The spi-install wiki page even suggests shorting the SPICLK GPIO to GND.

On the spi install wiki page, it’s not continuous shortcut. It’s just shortcut and remove.

Also, usually in bootrom or maskrom, after setting the registers and try to load and if failed, the code should restore the registers or the state for next loader, or the default power on state is not right.

I think that the wiki page you refer to may be somewhat out of date, or simply in error. In particular, look at page 12 of the rev. 1.3 schematic at the top center of the page, it is showing that GPIO2_A0, GPIO2_A1, I2C7_SDA, I2C7_SCL, GPIO2_B1, and GPIO2_B2 are pulled up to VCC_3V0 via 4.7k. Those 6 pins correspond to the line in the wiki about being pulled up to 3v3.

Nice caught, we will fix the wiki page.

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You are right. The schematic shows those pull-ups to be to 3V0. The wiki seems to have received an update, because it now states that those pull-ups go to 3V0 (which makes more sense :wink:)

Nobody says you can’t have a 2A buck for 3V0 :wink: … Anyway I guess 500mA would be plenty on that header.

True, but every design decision comes down to being a tradeoff between perfection and cost.

300 mA, minus whatever draw is already on it, and you never build a circuit to draw at its absolute limit. I’d say that realistically, you have about 150 mA of current available from VCC_3V0.

… which may still be enough. Now that I look at the raspberry pi specifications, they’re actually saying that their 3v3 can only supply about 50 mA.

And the fact that VCC_3V0 is from an LDO means that it would be a much better choice for things like sound cards or other noise sensitive peripherals.

True. But some things are worth their cost or are end up being even costlier. Now you either need a hat with (bidrectional!) voltage shifters (and you don’t see the nice coloured 40-pin no more), risk burning out your RK3399, or some series resistors.

The schematic says they need 13.5mA on 3V0, which leaves 280mA :wink:
But seriously, I can see an I2C level shifter, the I2C pull ups, and the supply to I/O banks – their current will depend on the output current of the pins, which will usually be only micro amps.

The 50mA the RPi spec says should definitely be possible. (But I agree, more would be nice. But realistically you wouldn’t need much more. Any HAT with more should use 5V and have a regulator on-board.)

But this way, I can’t even grab 3.0V as V_target for my serial cable :sob:

An LDO integrated into an PMIC with how many switching regulators? :slight_smile: That supply rail will be every thing but noiseless.

Update:

@lbdroidman Do you have any peripherals connected to the GPIOs? What would your preferred method of connecting them be? (Level shifter, series resistor, nothing, something else entirely?, integrated on a HAT?)

Maybe cut the 3V3 traces to pin 1 & 17 and re-wire them to 3V0? Because the only problem is that you don’t have 3V0 available to power external 3V3 peripherals (which should work fine @3V0)

I don’t actually use RockPi4. I use Rock960, which matches the 96boards CE specifications (for the most part). Its made by the same people, and its similar enough (virtually identical schematics), that nearly everything is applicable to both.

Except the I/O voltage, since 96boards specifies 1.8V I/O.

I have designed a number of mezzanine boards for 96boards CE that would work on the Rock960, including https://groupgets.com/campaigns/485-i2s-mezzanine

Note that on that particular board, the 2 DAC’s and the ADC require 3.3v for their analog sides, and 1.8v for their digital sides, so the 1.8v is supplied directly from the header, and the 3.3v is supplied by an L4931-3.3 from 5v on the header.

Ah, I see. I guess it’s like the Odroid XU4, which has a 1.8V GPIO header. There a riser card is offered with level shifters to go to either 3V3 or 5V0.

For 1.8V that makes sense because there is more 3V3-hardware (readily) available.

I’ll guess I’ll cut the traces and connect to either the internal 3V0 or add another 3V0 LDO.

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Most of the higher end hardware is all 1.8v now. Its more of entry level or older stuff that remains 3.3. Things that are more readily compatible with the pi/arduino perspectives.

Yea, sure. What I meant was 3v3-hardware is more available at retailers (at least in my country).

These are really sad news. With 3.0V GPIOs this 40 PIN connector is useless. Moreover there is a critical flaw in the project: How can you put 3.3V supply on GPIO header if the IOs are only 3.0V? Let’s say that probably 50% raspberry hats would work even on 3.0V, but in the actual scenario you can’t even connect a simple button or a switch, further you can’t even put a level shifter since no 3.0V is present on the header.

Unfortunately I am about to cancel the planned acquisition of the Rock Pi, luckily I didn’t burn the Rockchip as this would happen the very first moment. I shall wait the next version, or the solution of this issue.

The I/O’s on the SoC are tolerant to levels that are outside of their nominal voltages. You would certainly find that in fact, you do NOT smoke the SoC by applying 3.3v I/O on 3.0v pins. Further, your other 3.3v equipment will even recognize logic levels output by the 3.0v device.

Example: TI PCM5142 (Digital to Analog converter) supports 1.8v and 3.3v supply and I/O voltages. When configured to 3.3v, it has an absolute maximum rating of 3.9v, which is 0.6 volt above nominal. Along with this, it has an input logic high of 0.7VDD (i.e., 2.31 volt) and a minimum output logic high of 0.8VDD (i.e., 2.64v).

Note how high the absolute maximum is. Most devices have similar limits and can operate within a fairly wide range of conditions, including the RK3399 SoC, which probably has an absolute max (you can confirm with the datasheet) somewhere in the neighborhood of 3.6v. Certainly higher than the 3.3 supply voltage it provides to peripherals.

In other words; DON’T SWEAT IT. It will work.

Technically you are correct. Stresses below Absolute Maximum Rating won’t damage your device. And that is the only thing Absolute Maximum Ratings mean. In particular, they do not imply that the device will still be functional under those stresses. That is what the Recommended Operating Conditions are.

A device operated over Recommended Operating Conditions might work, it might not. It might deviate from specification (power consumption, temperature, max frequency, …) which might be ok for a specific situation or it might not.

Not knowing what exactly @Coyote’s plans are with the device and peripherals, whether or not it will be used in a commercial application/product and/or safety-critical I would not blindly recommending operating the Rock Pi above those stresses.

(Yes, I know you need to be one diode-drop voltage above I/O supply voltage of an I/O pin configured as input for any significant current to flow. Still, I protect those inputs with a series resistance of 1kΩ.)

In the future I plan to move all external electronics to 3.0V or at least feed the I/Os through a level shifter.

The behavior of a device operating between recommended and absolute may differ based on a number of different conditions. What you say is generally true – that nothing is guaranteed in that range, HOWEVER IN THIS CASE, running a slightly too high of a voltage will just cause the excess to be drained off by the diodes in the SoC (as you yourself said, it will be clamped to 3.15). It will definitely recognize 3.3v logic high and low. The only question is if the device he is connecting will properly recognize the slightly lower high levels that are output by the SoC, which frankly is almost an absolute guarantee.

And you also need to look at what @Coyote said to recognize the context. I’m not blindly recommending anything. He said “luckily I didn’t burn the Rockchip as this would happen the very first moment” – that line alone says a lot about his technical knowledge and his application.

First of all, if he was highly experienced, he wouldn’t have suggested that something would “burn”, because clearly that is not the case. Given his fairly noobie view, we can also determine that he is not a commercial vendor, rather a hobbyist. Further, the main goal of my statement to him is to help him to realize that nothing is going to catch on fire or otherwise be damaged by the connection of 3.3v peripherals to this board.

My intention was to replace Rpi 3 B with RockPi 4, for a specific industrial box. It shall communicate over I2C and UART, few other GPIOs are used for relay and LED. The board has its own 3.3V PSU. The first thing is that pull-ups of I2C are already soldered to 3V, meanwhile the board has two pull-ups connected to 3.3V, which is normal, as the RPi comes without pull-ups, just GPIOs that you have to configure and add pull uo/down according the use of GPIO. But this can be solved with desoldering pull-ups on the board or on RockPi, but I don’t find where are located.

Now what’s weird: The I2C pull-ups are connected to 3V, which makes sense. The SPI flash which should also have 3V level, is supplied with 3.3V ??!!

You also encourage users to use and test hats, shileds of the RPi for example the official Rpi LCD was tested and works flawlessly. But all these hats are designed for 3.3V, not 3V. In the same time you advise that GPIOs max voltage is 3.15V, it’s a little bit contradictory. The Hard Kernel guys say that the voltage may not exceed 3.15V, so their ODROID XU4 uses 1.8V level and you have to install a level shifter card.

If you planned to make a good Rpi clone then you should also make the GPIO connector as much similar to the original. The SPI for example has only one CE, that is shared with SPI flash. If you have a flash installed, then you can’t use SPI. Instead of second CE you out an analog input, which Rpi doesn’t have, you could make a second header with enhanced signals instead.

Anyway it seems that RockPi has a big potential, but it needs testing and some review from Rockchip engineer would be welcome. There is no information about internal structure of GPIOs, not the absolute maximum ratings. If the input is overvolted it can cause damage, slow damage not seen in a quick test.

No. It does NOT have an absolute maximum of 3.15. It CLAMPS to 3.15. Think about how zener diodes work.

I’m not concerned by voltage levels. My concern is the voltage clamping itself. Because a clamped voltage means there is as much current flowing as the source can deliver. Even if the difference is just 150mV. And the absolute value of the current isn’t necessarily important either. 10mA, depending on the chip can be enough to burn an I/O pin (or rather it’s driver circuitry). And if you’re unlucky take the whole I/O port with it. Or everything connected to the I/O-rail (if your chip has a dedicated I/O voltage rail). Or the whole chip.
Technically the current isn’t the problem either. It all depends on how much energy, heat, the I/O driver is able to handle. Technically just the high side switch of the I/O driver. Because that’s the parasitic pn-junction (aka diode), the current has to go through to be clamped to the I/O voltage. If your source can supply enough current you can also raise the I/O voltage this way to damage your chip.
That is all to say that, if you (not you specifically, generally a person) don’t already know all this and have at least a rudimentary understanding of what is going on (I believe you do), then I would not recommend a person do this. Because you don’t generally know what people are going to connect. And I’m not talking about @Coyote, specifically, but other people might read this too and connect god-knows-what. That’s what I’m thinking about …

Anyway. I think I said that already, but I have a 1kOhm resistor between the 3.0V GPIO and the 3.3V external signal. That gives me 3mA of clamp current, or just 1.5mA if the GPIO is clamped to 3.15V. I would have gone higher, but with the serial debug (that’s what I connnected) running at 1.5Mbps, I was worried about signal integrity.

While maybe technically not necessary, the Angst resistor (that’s the German technical term for this kind of resistor: a resistor you put in out of fear :wink: ) just gives me piece of mind. Because if the FTDI USB-UART is configured 25mA (or whatever it can do in its high current output mode) it can easily blow out the RK3399’s measly 4mA (or at least I think they are that weak) I/Os.

Ok, I. should have been more specific. I wasn’t just talking about @Coyote, but other audiennce that might stumble upon this topic as well.

His choice of the word “burn” isn’t too far off. I would use it too. But then I would assume you would not burn chip, but the I/O, maybe the bank (assuming the I/O rail wouldn’t rise above it’s absolute maximum rating.

All well and good, but you’t be sure that the 3.3V won’t damage anything. Actually, Rockchip says anything above 3.15V might damage the chip or parts of it. Why not recommend at least a current limiting resistor or a level shifter? With a level shifter you can connnect 5V peripherals too …

@lbdroidman: See what I mean? Industrial box! (I have no idea why someone would do that, but that’s the world we live in…)

Jup. Especially since the SPI flash has a supply range of 2.7 - 3.6V. I think electrial engineers are just too accustomed to the 3.3V rail :wink:
Thanks for catching that. I’ll fix my RockPi.

I agree, but that issue is documented and (at least for me) not such a big deal. I plan to make a change similar to what you described once the issue becomes pressing for me.

And what happens to a zener when the source is not current limited? :wink:

Anyway I just had a looksy in the datasheet. I figured Rockchip ought to know what’s what.
http://rockchip.fr/RK3399%20datasheet%20V1.8.pdf

Chapter 3, page 65, ff. Maximum supply voltage of a 3.0V rail: 3.15V, Max input voltage: 3.15V.
Btw, “clamping” for me implies limiting. the voltage to protect something. Like a crowbar. That is not the case here. The clamping is simply a side-effect of the parasitic pn-junction and a too-high of a current will damage that and the transistor. At least that GPIO will be broken. If the failure mode is continuity (which it usually is), depending on the strength of the source, more of the chip might be damaged.