The number of L1 Dcache Refills is obtained by directly reading the PMU counter, but the result is always 0. The relevant register enable configuration is as follows：
asm volatile(“mrs %0, pmcr_el0” : “=r”(pmcr));
pmcr |= (1UL << 0) /* E: enable all counters /
| (1UL << 1) / P: reset event counters /
| (1UL << 2); / C: reset cycle counter */
asm volatile(“msr pmcr_el0, %0” :: “r”(pmcr));
asm volatile(“isb”);
asm volatile(“MSR PMCNTENSET_EL0, %0” : : “r” (value));
value = 0 & 0x1F;
asm volatile(“MSR PMSELR_EL0, %0” : : “r” (value));
value = 0x03;
asm volatile(“MSR PMXEVTYPER_EL0, %0” : : “r” (value));
