Early boot loop with USB A TTL cable

rs38 · October 31, 2024, 9:59pm

pretty sure, it’s a power fail, Notebook’s USB seem to drop to 4v or 4,5v when powered on.
would be a very nice and handy solution to check status and power on.

Does it depend on the equippment of the Rock? Amount of RAM eMMC etc.?
Tested with Rock3A and 4B+ both 2GB

channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
DDR Version 1.25 20210517
In
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
DDR Version 1.25 20210517
In
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
DDR Version 1.25 20210517
In
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
DDR Version 1.25 20210517
In
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB
256B stride
channel 0
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 1
CS = 0
MR0=0x19
MR4=0x3
MR5=0x6
MR8=0x8
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0xFF
channel 0 training pass!
channel 1 training pass!

rs38 · October 31, 2024, 10:04pm

this is over a USBC->USBA converter cable that shows stable 5v:

the read training result:
DQS0:0x34, DQS1:0x33, DQS2:0x33, DQS3:0x32,
min  : 0xd  0xf 0x11  0xd  0x1  0x7  0x9  0x5 , 0xa  0x7  0x2  0x1  0xd  0xc  0xd  0x8 ,
      0x11  0xf  0xd  0xb  0x2  0x2  0x5  0x5 , 0xf  0xb  0x8  0x3 0x11 0x12  0xf 0x12 ,
mid  :0x28 0x2a 0x2c 0x29 0x1d 0x21 0x25 0x21 ,0x25 0x22 0x1c 0x1c 0x28 0x26 0x28 0x23 ,
      0x2b 0x2a 0x25 0x24 0x1c 0x1b 0x1e 0x1f ,0x29 0x25 0x22 0x1e 0x2c 0x2d 0x2a 0x2d ,
max  :0x44 0x45 0x48 0x45 0x39 0x3b 0x41 0x3d ,0x40 0x3d 0x37 0x37 0x44 0x41 0x43 0x3e ,
      0x46 0x46 0x3e 0x3d 0x36 0x35 0x37 0x39 ,0x43 0x3f 0x3d 0x39 0x48 0x48 0x45 0x48 ,
range:0x37 0x36 0x37 0x38 0x38 0x34 0x38 0x38 ,0x36 0x36 0x35 0x36 0x37 0x35 0x36 0x36 ,
      0x35 0x37 0x31 0x32 0x34 0x33 0x32 0x34 ,0x34 0x34 0x35 0x36 0x37 0x36 0x36 0x36 ,
the write training result:
DQS0:0x2f, DQS1:0x1d, DQS2:0x22, DQS3:0xa,
min  :0x75 0x77 0x7a 0x78 0x69 0x6d 0x6f 0x71 0x70 ,0x60 0x5f 0x5a 0x59 0x66 0x65 0x63 0x63 0x5e ,
      0x69 0x69 0x63 0x63 0x5b 0x59 0x5a 0x60 0x5f ,0x4f 0x4d 0x4d 0x48 0x56 0x55 0x50 0x58 0x4c ,
mid  :0x91 0x93 0x95 0x93 0x84 0x88 0x8b 0x8b 0x8a ,0x7b 0x7a 0x73 0x72 0x81 0x7e 0x7d 0x7c 0x78 ,
      0x85 0x85 0x7d 0x7e 0x77 0x73 0x75 0x7a 0x7a ,0x6a 0x68 0x67 0x61 0x71 0x70 0x6c 0x72 0x68 ,
max  :0xae 0xb0 0xb1 0xae 0xa0 0xa4 0xa7 0xa5 0xa5 ,0x97 0x95 0x8c 0x8c 0x9c 0x97 0x97 0x95 0x92 ,
      0xa1 0xa1 0x97 0x99 0x94 0x8e 0x91 0x95 0x95 ,0x86 0x84 0x81 0x7b 0x8d 0x8c 0x88 0x8d 0x84 ,
range:0x39 0x39 0x37 0x36 0x37 0x37 0x38 0x34 0x35 ,0x37 0x36 0x32 0x33 0x36 0x32 0x34 0x32 0x34 ,
      0x38 0x38 0x34 0x36 0x39 0x35 0x37 0x35 0x36 ,0x37 0x37 0x34 0x33 0x37 0x37 0x38 0x35 0x38 ,
CA Training result:
cs:0 min  :0x49 0x46 0x3e 0x36 0x3e 0x34 0x40 ,0x4b 0x42 0x3e 0x38 0x3e 0x37 0x43 ,
cs:0 mid  :0x85 0x86 0x7a 0x77 0x79 0x74 0x6d ,0x88 0x83 0x7a 0x77 0x79 0x78 0x70 ,
cs:0 max  :0xc2 0xc7 0xb7 0xb8 0xb5 0xb5 0x9a ,0xc5 0xc4 0xb7 0xb6 0xb5 0xb9 0x9d ,
cs:0 range:0x79 0x81 0x79 0x82 0x77 0x81 0x5a ,0x7a 0x82 0x79 0x7e 0x77 0x82 0x5a ,
out

U-Boot SPL latest-2023.07.02-3-b1eb2bde-gb1eb2bde (Aug 29 2023 - 10:43:04 +0000)
DDR V1.16 6f71c736ce typ 23/03/02-20:01:48
In
LP4/4x derate en, other dram:1x trefi
ddrconfig:0
LPDDR4X, 324MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
tdqss: cs0 dqs0: 24ps, dqs1: -72ps, dqs2: -48ps, dqs3: -144ps,

change to: 324MHz
PHY drv:clk:36,ca:36,DQ:29,odt:0
vrefinner:24%, vrefout:41%
dram drv:40,odt:0
clk skew:0x62

change to: 528MHz
PHY drv:clk:36,ca:36,DQ:29,odt:0
vrefinner:24%, vrefout:41%
dram drv:40,odt:0
clk skew:0x58

change to: 780MHz
PHY drv:clk:36,ca:36,DQ:29,odt:0
vrefinner:24%, vrefout:41%
dram drv:40,odt:0
clk skew:0x58

change to: 1560MHz(final freq)
PHY drv:clk:36,ca:36,DQ:29,odt:60
vrefinner:16%, vrefout:22%
dram drv:40,odt:80
vref_ca:00000071
clk skew:0x26
cs 0:
the read training result:
DQS0:0x34, DQS1:0x33, DQS2:0x34, DQS3:0x32,
min  : 0xe  0xf 0x11  0xe  0x2  0x7  0x9  0x5 , 0xa  0x7  0x2  0x2  0xd  0xc  0xd  0x8 ,
      0x12 0x12  0xd  0xb  0x3  0x2  0x5  0x5 , 0xe  0xb  0x7  0x2 0x10 0x12  0xf 0x11 ,
mid  :0x29 0x2a 0x2c 0x29 0x1d 0x21 0x25 0x21 ,0x25 0x22 0x1c 0x1c 0x28 0x27 0x27 0x23 ,
      0x2c 0x2c 0x26 0x24 0x1d 0x1c 0x1e 0x1f ,0x28 0x25 0x22 0x1d 0x2b 0x2d 0x2a 0x2d ,
max  :0x44 0x45 0x48 0x44 0x39 0x3c 0x41 0x3d ,0x41 0x3d 0x37 0x37 0x44 0x42 0x42 0x3e ,
      0x47 0x46 0x3f 0x3e 0x37 0x36 0x38 0x3a ,0x42 0x3f 0x3d 0x39 0x46 0x48 0x45 0x49 ,
range:0x36 0x36 0x37 0x36 0x37 0x35 0x38 0x38 ,0x37 0x36 0x35 0x35 0x37 0x36 0x35 0x36 ,
      0x35 0x34 0x32 0x33 0x34 0x34 0x33 0x35 ,0x34 0x34 0x36 0x37 0x36 0x36 0x36 0x38 ,
the write training result:
DQS0:0x2a, DQS1:0x18, DQS2:0x1d, DQS3:0xa,
min  :0x6f 0x72 0x74 0x72 0x63 0x69 0x6b 0x6b 0x6b ,0x5c 0x5a 0x54 0x54 0x61 0x5e 0x5e 0x5e 0x59 ,
      0x65 0x65 0x60 0x60 0x59 0x55 0x58 0x5d 0x5d ,0x4f 0x4d 0x4c 0x48 0x56 0x55 0x50 0x58 0x4d ,
mid  :0x8b 0x8e 0x90 0x8d 0x7e 0x83 0x86 0x84 0x84 ,0x77 0x75 0x6d 0x6e 0x7c 0x79 0x78 0x77 0x73 ,
      0x81 0x81 0x7a 0x7a 0x74 0x6f 0x72 0x77 0x78 ,0x6a 0x68 0x66 0x61 0x71 0x70 0x6c 0x72 0x68 ,
max  :0xa8 0xaa 0xac 0xa8 0x99 0x9d 0xa1 0x9e 0x9d ,0x92 0x91 0x87 0x88 0x97 0x94 0x93 0x90 0x8e ,
      0x9d 0x9d 0x95 0x95 0x8f 0x8a 0x8c 0x91 0x93 ,0x86 0x84 0x81 0x7b 0x8d 0x8c 0x88 0x8d 0x84 ,
range:0x39 0x38 0x38 0x36 0x36 0x34 0x36 0x33 0x32 ,0x36 0x37 0x33 0x34 0x36 0x36 0x35 0x32 0x35 ,
      0x38 0x38 0x35 0x35 0x36 0x35 0x34 0x34 0x36 ,0x37 0x37 0x35 0x33 0x37 0x37 0x38 0x35 0x37 ,
CA Training result:
cs:0 min  :0x49 0x46 0x3e 0x36 0x3e 0x34 0x40 ,0x4b 0x42 0x3e 0x38 0x3e 0x37 0x43 ,
cs:0 mid  :0x85 0x86 0x7a 0x77 0x7a 0x74 0x6c ,0x88 0x83 0x7a 0x77 0x79 0x78 0x70 ,
cs:0 max  :0xc2 0xc7 0xb6 0xb9 0xb6 0xb5 0x99 ,0xc5 0xc4 0xb7 0xb7 0xb5 0xb9 0x9d ,
cs:0 range:0x79 0x81 0x78 0x83 0x78 0x81 0x59 ,0x7a 0x82 0x79 0x7f 0x77 0x82 0x5a ,
out

U-Boot SPL latest-2023.07.02-3-b1eb2bde-gb1eb2bde (Aug 29 2023 - 10:43:04 +0000)