Hi everyone,
I’m trying to get a custom NixOS image booting on my Radxa E52C board and I’m running into a kernel hang very early in the boot process. I’ve successfully built a custom U-Boot and can get the kernel to start loading, but it always hangs. I’m hoping someone with more experience with this board’s hardware specifics can point me in the right direction.
My Setup:
- Board: Radxa E52C (RK3582)
- OS: NixOS, building a custom image.
- Kernel: Mainline Linux 6.15.4 (from Nixpkgs).
-
U-Boot: Based on Collabora’s RK3588 fork (
cbc9673f
), with ATF and TPL prerequisites. -
Device Tree: I am using the
rk3582-radxa-e52c.dts
from the mainline kernel source.- Link to the mainline DTS
The Problem:
The system boots through my custom U-Boot, which successfully loads the kernel, initrd, and the device tree blob. The kernel begins to boot, but it consistently hangs at the exact same point.
Here is the final output from the serial console (loglevel=8
):
Using mainline DTS:
[ 0.351430] kvm [1]: GIC system register CPU interface enabled
[ 0.352000] kvm [1]: vgic interrupt IRQ18
[ 0.352427] kvm [1]: VHE mode initialized successfully
[ 0.467092] Initialise system trusted keyrings
[ 0.467932] workingset: timestamp_bits=42 max_order=21 bucket_order=0
[ 0.473809] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.475056] 9p: Installing v9fs 9p2000 file system support
[ 0.514559] Key type asymmetric registered
[ 0.514954] Asymmetric key parser 'x509' registered
[ 0.515584] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 244)
[ 0.516541] io scheduler mq-deadline registered
[ 0.516979] io scheduler kyber registered
[ 0.576919] Freeing initrd memory: 9868K
[ 0.578787] ledtrig-cpu: registered to indicate activity on CPUs
[ 0.599949] dma-pl330 fea10000.dma-controller: Loaded driver for PL330 DMAC-241330
[ 0.600670] dma-pl330 fea10000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[ 0.602720] dma-pl330 fea30000.dma-controller: Loaded driver for PL330 DMAC-241330
[ 0.603438] dma-pl330 fea30000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[ 0.605487] dma-pl330 fed10000.dma-controller: Loaded driver for PL330 DMAC-241330
[ 0.606204] dma-pl330 fed10000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[ 0.620177] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.622808] printk: legacy console [ttyS2] disabled
[ 0.623462] feb50000.serial: ttyS2 at MMIO 0xfeb50000 (irq = 38, base_baud = 1500000) is a 16550A
-- HANGS HERE and causes a board reset--
When using vendor DTS:
...
[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000101390000
[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[ 0.000000] rockchip_cpuclk_pre_rate_change: Invalid rate : 1100000000 for cpuclk
[ 0.000000] clk: couldn't set armclk_l clk rate to 1100000000 (-16), current rate: 816000000
-- HANGS HERE --
What I’ve Tried:
-
Using the Vendor DTB: I extracted the
.dtb
from the official Radxa Debian image for the E52C and used it with my mainline kernel. This resulted in the exact sameInvalid rate : 1100000000 for cpuclk
error, indicating a mismatch between what the vendor DTB requests and what the mainline kernel’s clock driver supports. -
Modifying the Vendor DTB:
- I decompiled the vendor DTB and commented out all CPU Operating Performance Points (OPP tables) except for the lowest frequency, hoping to force a safe clock rate. The error remained unchanged.
- I also tried removing the
assigned-clocks
andassigned-clock-rates
properties from all CPU nodes. This also did not change the outcome.
-
Disabling Peripherals: I systematically disabled major peripherals in the device tree (
PCIe
,GMAC
,SATA
,GPU
, etc.). This had no effect on the crash point.
My Questions:
- Is this
Invalid rate : 1100000000 for cpuclk
error a known issue when running a recent mainline kernel on the RK3582? - Does the mainline kernel require a specific patch for the E52C’s clock or PMIC configuration that I might be missing?
- Are there any specific kernel config options (
CONFIG_*
) that are essential for this board that might not be enabled in a standard mainline configuration?
It seems like there’s a fundamental incompatibility between the mainline kernel’s clock driver and the hardware/firmware expectations. Any advice on what to investigate next or which part of the device tree might be causing this would be greatly appreciated.
Thanks