DSI Timings mismatch in Radxa on AOSP

#1

Hi, I am trying to interface and add support of waveshare 7 inch c panel for my radxa cm3 AOSP Build-

Although I am able to get the display to enable, backlit and show picture, there’s a strange offset, that just can’t seem to go.
The display is wrapping around weirdly.

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When referencing the port of raspberry pi 7 inch display I found the timings are different than upstream drivers and going more level I realized that de-mipi-dsi.c seems to handle the display timings different than raspberry pi.

for reference of raspberry pi display -
Radxa Version :
static const struct drm_display_mode raspits_tc358762_mode = {
.clock = 26101800 / 1000,
.hdisplay = 800,
.hsync_start = 800 + 1,
.hsync_end = 800 + 1 + 2,
.htotal = 800 + 1 + 2 + 52,
.vdisplay = 480,
.vsync_start = 480 + 7,
.vsync_end = 480 + 7 + 2,
.vtotal = 480 + 7 + 2 + 21,
.vrefresh = 60,
.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
};
Raspberry Pi Version :
static const struct drm_display_mode raspberrypi_7inch_mode = {
.clock = 30000,
.hdisplay = 800,
.hsync_start = 800 + 131,
.hsync_end = 800 + 131 + 2,
.htotal = 800 + 131 + 2 + 45,
.vdisplay = 480,
.vsync_start = 480 + 7,
.vsync_end = 480 + 7 + 2,
.vtotal = 480 + 7 + 2 + 22,
.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
};

Now My problem is, that I have tried so many iterations like literally for a week, and I am stuck as I think it’s an issue with the calculation of timings itself.

My Display has the following timings -


Waveshare 7 Inch C Panel

–
static const struct drm_display_mode ws_panel_7_0_c_mode = {
.clock = 50000,
.hdisplay = 1024,
.hsync_start = 1024 + 100,
.hsync_end = 1024 + 100 + 100,
.htotal = 1024 + 100 + 100 + 100,
.vdisplay = 600,
.vsync_start = 600 + 10,
.vsync_end = 600 + 10 + 10,
.vtotal = 600 + 10 + 10 + 10,
};

static const struct ws_panel_data ws_panel_7_0_c_data = {
.mode = &ws_panel_7_0_c_mode,
.lanes = 2,
.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
};

Can Anyone from Radxa team can look into this and tell why are timings different than raspberry pi and what’d be the compatible timings for this waveshare panel that’ll make the wrap go away.

Thanks

8 Inch Display on CM3
#2

@luffy @nasca can you please help ?

#3

@nasca , can you please help, I am unable to move forward and project is stuck now, as not even the 8 inch display is working with cm3 AOSP

#4

Did you enabled the HDMI as the same time? CM3 can only support one display. You need to disable HDMI and enable MIPI only.

#5

Hello Jack,
although I didn’t but I was facing this issue with vp0 and vp1 routing for hdmi and dsi, so i was in begining not able to get picture on dsi panel, and I solved it by fixing the panel routing as follows-

&route_dsi1 {
status = “okay”;
connect = <&vp0_out_dsi1>;
};

&video_phy1 {
status = “okay”;
};

&dsi1_in_vp0 {
status = “okay”;
};

&dsi1_in_vp1 {
status = “disabled”;
};

&hdmi_in_vp1 {
status = “okay”;
};

and I am able to get picture on dsi panel, but it’s shifted as shown in image