Hi,
I am experiencing some DDR training problems and I suspect it’s one RAM chip that’s affected because of some tests I did. I would like to modify the DDR training blob using ddrbin_tool and boot_merger tools, but have no idea which settings to set to be able to do ddr training for a particular channel or chip. The one that should be disabled is CH2. If there is a hardware solution to disable the channel, I am also open to that. I am not interested in replacing the IC, because one channel is enough for me to continue my tests.
the logs for current ddr training:
`DDR 9fa84341ce typ 24/09/06-09:51:11,fwver: v1.18
ch0 ttot10
ch0 ttot10
ch1 ttot10
ch2 ttot10
ch3 ttot10
ch0 ttot16
LPDDR4, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
ch1 ttot16
channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
ch3 ttot16
channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
Manufacturer ID:0xff
ch:2 dq0 fail,write:0x1,read:0x2
ch:2 dq1 fail,write:0x2,read:0x4
ch:2 dq2 fail,write:0x4,read:0x8
ch:2 dq3 fail,write:0x8,read:0x10
ch:2 dq4 fail,write:0x10,read:0x20
ch:2 dq5 fail,write:0x20,read:0x0
ch:2 dq6 fail,write:0x40,read:0x80
ch:2 dq7 fail,write:0x80,read:0x0
ch:2 dq8 fail,write:0x100,read:0x200
ch:2 dq9 fail,write:0x200,read:0x400
ch:2 dq10 fail,write:0x400,read:0x800
ch:2 dq11 fail,write:0x800,read:0x1000
ch:2 dq12 fail,write:0x1000,read:0x2000
ch:2 dq13 fail,write:0x2000,read:0x4000
ch:2 dq14 fail,write:0x4000,read:0x8000
ch:2 dq15 fail,write:0x8000,read:0x0
ch:2 dq0 fail,write:0xfffffffe,read:0xffbfffbd
ch:2 dq1 fail,write:0xfffffffd,read:0xffbfffbb
ch:2 dq2 fail,write:0xfffffffb,read:0xffbfffb7
ch:2 dq3 fail,write:0xfffffff7,read:0xffbfffaf
ch:2 dq4 fail,write:0xffffffef,read:0xffbfff9f
ch:2 dq5 fail,write:0xffffffdf,read:0xffbfffbf
ch:2 dq6 fail,write:0xffffffbf,read:0xffbfff3f
ch:2 dq7 fail,write:0xffffff7f,read:0x0
ch:2 dq8 fail,write:0xfffffeff,read:0xffbffdbf
ch:2 dq9 fail,write:0xfffffdff,read:0xffbffbbf
ch:2 dq10 fail,write:0xfffffbff,read:0xffbff7bf
ch:2 dq11 fail,write:0xfffff7ff,read:0xffbfefbf
ch:2 dq12 fail,write:0xffffefff,read:0xffbfdfbf
ch:2 dq13 fail,write:0xffffdfff,read:0xffbfbfbf
ch:2 dq14 fail,write:0xffffbfff,read:0xffbf7fbf
ch:2 dq15 fail,write:0xffff7fff,read:0x0
error
ERR`
Any insight is appreciated.
Thanks.
Update: It is possible to mask other DRAM banks using channel mask parameter from the DDR training blob.
-
Get rkbin tools and binaries from rockchip repo
-
Extract the parameter files from the DDR loader using ddrbin_tool (manual is in the repo)
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Edit the mask for the desired channel (the one to be used) (i.e., channel mask = 1 for ch0)
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Generate the modified one using ddrbin_tool.
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Build the SPL loader with the modified DDR loader using bootmerger tool.
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Next is to modify u-boot and change the maximum allowed SDRAM, found in
"include/configs/rk3588_common.h":SDRAM_MAX_SIZE, I set it toSDRAM_MAX_SIZE = 0x3c000000; -
Build u-boot and flash as (in maskrom):
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`rkdeveloptool db modifed_spl_loader_masked_channel.bin
-
rkdeveloptool wl 64 idbloader.img && rkdeveloptool wl 16384 u-boot.itbPreSerial: 2, raw, 0xfeb50000 This is DRAM: 958 MiB Sysmem: init Relocation Offset: 39a1e000 Relocation fdt: 379f9140 - 379fecb0 CR: M/C/I Bad memblk0: 0x3c000000 - 0xff140000 Using default environment Hotkey: ctrl+ mmc@fe2c0000: 1, mmc@fe2e0000: 0 Bootdev(atags): mmc 0 MMC0: HS200, 200Mhz PartType: EFI DM: v2 No misc partition boot mode: normal FIT: No boot partition No resource partition No resource partition Failed to load DTB, ret=-19 No find valid DTB, ret=-22 Failed to get kernel dtb, ret=-22 In: serial Out: serial Err: serial
I get only 1GB detected instead of 4GB, so it may just be me who messed up something along the way, but I am glad I brought back my board from the dead. I will update once more if I figure it out.
This setup can also workaround boards with DRAM chips of different sizes.