Basic question about Rock 2a IOMUX

#1

I am looking to design an expansion card for the Rock 2a, and I don’t understand the terminology used in the GPIO pin header. Specifically referencing the hardware interface 40 pin GPIO header at https://docs.radxa.com/en/rock2/rock2a/hardware-design/hardware-interface

Question 1. This map shows the 40 pin header with up to 4 additional functions for each pin. However, some of the peripherals have _M0 and _M1 after them. What does this mean?

For example, pin 27 and 28, function 3 is UART3_RSTN and UART3_CSTN respectively. But there is no UART3_TX, only UART3_TX_M0 or UART3_TX_M1. Does this mean the RST/CST pins will work with both the _M0 and _M1 varieties, or with neither?

Question 2: Pins 8 and 10 show UART2_TX_M0/UART2_RX_M0 highlighted in orange. What does this mean? What is the significance of UART2?

Question 3: I am looking for a 3rd UART beyond UART2 and UART3. The only other available UART on the header that has both Rx and Tx brought out is UART1 on pins 7 and 15, but that has UART1_TX_M0 and UART1_RX_M1. Can I combine M0 and M1 labels to make a working UART1 port?

If there is a document I should read that explains how this works please tell me where to go. I have been looking for the answers and I can’t find it anywhere.

#2

To answer Q1 and Q3:
Each bus has a different channel, such as M0/M1, etc., each channel is mutually exclusive, with the M0 channel, you can not use the M1 channel, because they can not share the same bus, such as, you open the I2C0_M1, then you turn on the I2C0_M0, the two I2C0 will force the use of resources! UART1_M0 and UART_M1 as you mentioned in Q3 are can’t be used together.
About UART3_RSTN and UART3_CSTN, I need to see exactly what’s going on before I answer you.

1 Like
#3

Q2: PIN_8 and PIN_10 are the common debug serial ports.

1 Like
#4

UART3_RSTN and UART3_CSTN can be used with UART3_M0 and UART3_M1, but UART3_M0 and UART3_M1, you can only choose one of them.

1 Like