Hi everyone,
I’m sharing an engineering paper about adapting a PP-OCRv6-based RapidOCR pipeline to the Allwinner A733 / Vivante VIP9000 NPU. Physical testing was on an Orange Pi Zero 3W, not a Radxa Cubie board. I’m posting here because the A733/VIPLite conversion and validation lessons may interest Cubie developers; this is not a claim of verified Radxa compatibility.
Paper and implementation guide: GitHub - sog777/orange-pi-zero-3w-rapidocr-npu: Engineering paper on porting RapidOCR / PP-OCRv6 to the Orange Pi Zero 3W A733/Vivante VIP9000 NPU, including graph rewrites, CPU verification, accuracy tests, and rejected full-NPU experiments. · GitHub
The conversion path was ONNX → ACUITY → NBG → VIPLite. The paper covers static model shapes, targeted convolution and LayerNorm graph rewrites, quantization, isolated arithmetic investigations, simulator-versus-hardware comparisons, and repeated physical execution.
Public source supplement — published 17 October 2026
The corrected engineering guide and source supplement are now public:
The supplement includes 3,143 readable source records and 2,523 retained command records, plus graph rewrite scripts, the VIPLite bridge/runtime, Visual AI integration, validation reports, model provenance and checksums. Commands are placed beside the relevant engineering stages in the guide. Public paths use /home/user/rapidocr-npu; adapt the account home before installation.
Corrections include refreshed manifest byte counts/hashes, completed Visual AI integration notes, installing the systemd user service before enabling it, a true byte comparison before the self-test reports byte-exact output, and corrected camera-recovery paths.
Not distributed: original test/camera images, proprietary vip_lite.h, 312 vendor-generated C/header files with unverified redistribution terms, and both compiled NBG model files. Their conditional build/validation commands remain documented; compatible authorized SDK components, locally generated outputs and separate image fixtures are required. Numeric parity tensors remain included.
The command record contains scripts, comments, fragments and intended commands; it is not a complete chronological terminal transcript. This is an engineering source supplement, not a tested fresh-install or turnkey backend. Hardware tests were not rerun for this publication revision. The deployed pipeline still uses canonical CPU recognition for every crop; rejected full-NPU experiments were not promoted. The 11.76 ms figure measures the native bridge call including associated transfer/cache work, not an isolated NPU kernel. No blanket reuse license has been assigned to project-authored code; third-party notices remain applicable.
A few findings:
- The detector used [1,3,736,736] input; the fixed-width recognizer used [1,3,48,320] with output [1,40,18710].
- Targeted graph changes included spatial-sampling rewrites for selected stride-2 convolutions, reshape/multiply/reduction projections, and LayerNorm Divide bypasses using reciprocal-square-root multiplication.
- Input-range correction and per-channel INT8 CNN weight quantization improved recognition. Successful import and compilation alone did not establish correct execution.
- One validated reference output matched simulator and hardware byte-for-byte. A repeated reference recognizer test passed 100 runs, with a median recognizer call of 13.36 ms. These results apply to specific fixtures and configurations, not arbitrary images.
The deployed result, integrated into Visual AI, remains NPU-supported and CPU-verified. Detection and eligible recognition attempts run on the NPU, while canonical ONNX Runtime CPU recognition checks every crop and supplies the final text and confidence scores. Wide lines and orientation classification remain on CPU.
A tested 18-line page took approximately 1.64–1.66 seconds on this verified path, including 18 NPU attempts and 18 CPU checks: 14 agreements and four corrections. CPU-reference agreement is not proof of perfect transcription, and no matched CPU-only speed advantage has been established.
The paper also covers higher-resolution tiled detection and rejected full-NPU experiments. One candidate reduced aggregate CPU consumption by approximately 77.65%, but increased processing time by approximately 79.34% and regressed accuracy, so it was not promoted.
The paper now has a public source and command supplement with conditional reproduction instructions. It is not an officially supported backend or a verified Radxa installation. The paper separates reported arithmetic observations from any unproven hardware or vendor root cause.
Feedback from others working with the A733/VIPLite stack is welcome, especially on graph conversion, quantization, and validation methodology.