For space reasons, this is our device tree:
/dts-v1/;
#include "rk3566-radxa-rock-3-compute-module.dtsi"
/ {
model = "Radxa CM3 RPI CM4 IO";
compatible = "radxa,radxa-cm3-rpi-cm4-io", "rockchip,rk3566";
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
regulator-name = "vcc_sd";
regulator-always-on;
};
imx219_vana_2v8: 2p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vana";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
imx219_vdig_1v8: 1p8v {
compatible = "regulator-fixed";
regulator-name = "camera_vdig";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
imx219_vddl_1v2: 1p2v {
compatible = "regulator-fixed";
regulator-name = "camera_vddl";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
cam24m: cam24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "cam24m";
};
};
&gpio_leds {
pi-led-green {
gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
default-state = "on";
pinctrl-0 = <&pi_led>;
};
pwr-led-red {
gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
default-state = "on";
pinctrl-0 = <&pwr_led>;
};
};
&sdmmc0 {
max-frequency = <150000000>;
supports-sd;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
sd-uhs-sdr104;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
status = "okay";
};
&pcie2x1 {
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
pinctrl-0 = <&pcie20m2_pins>;
status = "okay";
};
&pinctrl {
leds {
pi_led: pi-led {
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
pwr_led: pwr-led {
rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdcard {
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pinctrl {
cam {
camera_pwr: camera-pwr {
rockchip,pins =
/* camera power en */
<4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&gpio4 {
cam_power {
gpio-hog;
gpios = <RK_PC1 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2m1_xfer>;
imx219_1: imx219-1@10 {
status = "okay";
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&cru CLK_CAM0_OUT>;
clock-names = "xvclk";
VANA-supply = <&imx219_vana_2v8>;
VDIG-supply = <&imx219_vdig_1v8>;
VDDL-supply = <&imx219_vddl_1v2>;
power-domains = <&power RK3568_PD_VI>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
imx219_out1: endpoint {
status = "okay";
remote-endpoint = <&dphy2_in>;
data-lanes = <1 2>;
clock-noncontinuous;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
};
&i2c0 {
status = "okay";
imx219_2: imx219-2@10 {
status = "okay";
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&cru CLK_CAM1_OUT>;
clock-names = "xvclk";
VANA-supply = <&imx219_vana_2v8>;
VDIG-supply = <&imx219_vdig_1v8>;
VDDL-supply = <&imx219_vddl_1v2>;
power-domains = <&power RK3568_PD_VI>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
imx219_out2: endpoint {
status = "okay";
remote-endpoint = <&dphy1_in>;
data-lanes = <1 2>;
clock-noncontinuous;
link-frequencies = /bits/ 64 <456000000>;
};
};
};
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "disabled";
};
&csi2_dphy1 {
status = "okay";
/*
* dphy1 only used for split mode,
* can be used concurrently with dphy2
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx219_out2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp0_in>;
};
};
};
};
&csi2_dphy2 {
status = "okay";
/*
* dphy2 only used for split mode,
* can be used concurrently with dphy1
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx219_out1>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&mipi_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy2_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
data-lanes = <1 2>;
};
};
};
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy1_out>;
};
};
};
&rkisp_vir1 {
status = "okay";
port {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
isp1_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
data-lanes = <1 2>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp1_in>;
data-lanes = <1 2>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkcif {
status = "okay";
};