OpenWrt builds [testing]

Hello, i am developing openwrt for rk3328 dual Ethernet boards, and i came across rock-pi-e. I have started to port the uboot and kernel dts files. Since i don’t have the board, i need someone to test the builds and provide me with the UART log.

Thanks.

1 Like

Very good, where is the download link? :smiley:

inital boot test1: https://github.com/jayanta525/build-openwrt-nanopi-r1/raw/rk3328-nanopi-r2s/rockpi-e-openwrt/openwrt-rockchip-armv8-radxa_rockpi-e-ext4-sysupgrade.img.gz

please send the uart log to messages.

Hello, this is the log from power on to the end.

���<debug_uart>
U-Boot TPL 2020.04 (May 15 2020 - 17:02:13)
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=14 CS=1 Die BW=16 Size=512MB
Trying to boot from BOOTROM
Returning to boot ROM…
<debug_uart>
U-Boot SPL 2020.04 (May 15 2020 - 17:02:13 +0000)
Trying to boot from MMC2
NOTICE: BL31: v2.3():v2.3
NOTICE: BL31: Built : 15:56:43, Apr 20 2020
NOTICE: BL31:Rockchip release version: v1.2

U-Boot 2020.04 (May 15 2020 - 17:02:13 +0000) OpenWrt

Model: Radxa Rockpi E
DRAM: 510 MiB
PMIC: RK8050 (on=0x40, off=0x00)
MMC: rksdmmc@ff500000: 1, rksdmmc@ff520000: 0
Loading Environment from MMC… Card did not respond to voltage select!
*** Warning - No block device, using default environment

In: serial@ff130000
Out: serial@ff130000
Err: serial@ff130000
Model: Radxa Rockpi E
Net: eth0: ethernet@ff540000
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc0(part 0) is current device
Scanning mmc 0:1…
Found U-Boot script /boot.scr
714 bytes read in 2 ms (348.6 KiB/s)

Executing script at 00500000

37048 bytes read in 3 ms (11.8 MiB/s)
4030132 bytes read in 92 ms (41.8 MiB/s)
Uncompress lzma kernel into memmory…
Uncompressed size: 13269000 = 0XCA7808

Flattened Device Tree blob at 01f00000

Booting using the fdt blob at 0x1f00000
Loading Device Tree to 000000001df19000, end 000000001df250b7 … OK

Starting kernel …

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.4.39 (ubnt@senseio) (gcc version 8.4.0 (OpenWrt 0
[ 0.000000] Machine model: Radxa ROCK Pi E
[ 0.000000] earlycon: uart8250 at MMIO32 0x00000000ff130000 (options ‘’)
[ 0.000000] printk: bootconsole [uart8250] enabled
[ 0.000000] cma: Reserved 16 MiB at 0x000000001f000000
[ 0.000000] On node 0 totalpages: 130560
[ 0.000000] DMA32 zone: 2040 pages used for memmap
[ 0.000000] DMA32 zone: 0 pages reserved
[ 0.000000] DMA32 zone: 130560 pages, LIFO batch:31
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.0
[ 0.000000] percpu: Embedded 21 pages/cpu s48280 r8192 d29544 u86016
[ 0.000000] pcpu-alloc: s48280 r8192 d29544 u86016 alloc=21*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: detected: ARM erratum 845719
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 128520
[ 0.000000] Kernel command line: console=ttyS2,1500000 console=tty1 earlycon9
[ 0.000000] Dentry cache hash table entries: 65536 (order: 7, 524288 bytes, )
[ 0.000000] Inode-cache hash table entries: 32768 (order: 6, 262144 bytes, l)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 473396K/522240K available (7934K kernel code, 542K rwdat)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 ji.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] random: get_random_bytes called from start_kernel+0x29c/0x394 wi0
[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycless
[ 0.000007] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398s
[ 0.001355] Console: colour dummy device 80x25
[ 0.001819] printk: console [tty1] enabled
[ 0.002204] printk: bootconsole [uart8250] disabled

1 Like

seems bootconsole got disabled, will enable that. did you try connecting to eth0 port and check if RockPi E is reachable at 192.168.1.1/24?

could you please format the log next time.

kernel started, and that’s a good sign.

It should find the mmc, mount rootfs and boot normally.

please ping to 192.168.1.1/24 through eth0. if DHCP fails. set any ip in the network 192.168.1.0/24 other than 192.168.1.1.

Thanks.

Hi jayanta525, @jayanta525 I ported the rock-pi-e in openwrt, there still issues when boot with idbloader.img+uboot.itb, please refer to the relevant link:
OP pull: https://github.com/openwrt/openwrt/pull/2945
My repo: https://github.com/hbl0307106015/openwrt/tree/rk3328
Below is the error log:

U-Boot TPL 2020.04 (May 10 2020 - 06:47:07)
spl_early_init
rk3328_dmc_init phy ff400000 pctrl ff780000 grf ff100000 cru ff440000 msch ff720000 ddr_grf ff798000
Starting SDRAM initialization...
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=14 CS=1 Die BW=16 Size=512MB
SPL malloc() before relocation used 0x5e8 bytes (1 KB)
>>TPL: board_init_r()
spl_init
Trying to boot from BOOTROM
Returning to boot ROM...
<debug_uart> 
spl:debug uart enabled in board_init_f
spl_early_init
clk_set_defaults()
clk_set_default_parents: could not read assigned-clock-parents for 3fc030
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: reg-offset: (not found)
ofnode_read_u32: reg-shift: x (2)
ofnode_read_u32: reg-io-width: x (4)
fdtdec_get_int: #clock-cells: x (1)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
PLL at ff440000: fbdiv=75, refdiv=1, postdiv1=3,              postdiv2=1, vco=1800000 khz, output=600000 khz
PLL at ff440060: fbdiv=96, refdiv=1, postdiv1=4,              postdiv2=1, vco=2304000 khz, output=576000 khz
PLL at ff440040: fbdiv=99, refdiv=2, postdiv1=2,              postdiv2=1, vco=1188000 khz, output=594000 khz
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
clk_of_xlate_default(clk=3fbd78)
clk_request(dev=3fc2c0, clk=3fbd78)
clk_get_rate(clk=3fbd78)
ofnode_read_u32: clock-frequency: x (24000000)
clk_set_defaults(serial@ff130000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc1d0
ofnode_read_prop: assigned-clock-rates: <not found>

U-Boot SPL 2020.04 (May 10 2020 - 06:47:07 +0000)
SPL malloc() before relocation used 0xbd0 bytes (2 KB)
>>SPL: board_init_r()
spl_init
board_spl_was_booted_from: brom_bootdevice_id 5 maps to '/rksdmmc@ff500000'
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (4)
ofnode_read_bool: non-removable: false
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff500000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc468
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff0000)
clk_request(dev=3fc2c0, clk=3ff0000)
clk_set_rate(clk=3ff0000, rate=400000)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (8)
ofnode_read_bool: non-removable: true
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff520000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc790
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff00a8)
clk_request(dev=3fc2c0, clk=3ff00a8)
clk_set_rate(clk=3ff00a8, rate=400000)
Trying to boot from MMC1
blk_find_device: if_type=6, devnum=0: rksdmmc@ff500000.blk, 6, 0
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
dwmci_send_cmd: Response Timeout.
Sending CMD55
Sending CMD41
Sending CMD55
dwmci_send_cmd: Response Timeout.
Sending CMD0
Sending CMD1
dwmci_send_cmd: Response Timeout.
Card did not respond to voltage select!
spl: mmc init failed with error: -95
Trying to boot from MMC1
blk_find_device: if_type=6, devnum=0: rksdmmc@ff500000.blk, 6, 0
clock is disabled (0Hz)
Buswidth = 1, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
dwmci_send_cmd: Response Timeout.
Sending CMD0
Sending CMD1
dwmci_send_cmd: Response Timeout.
Card did not respond to voltage select!
spl: mmc init failed with error: -95
Trying to boot from MMC2
blk_find_device: if_type=6, devnum=1: rksdmmc@ff500000.blk, 6, 0
blk_find_device: if_type=6, devnum=1: rksdmmc@ff520000.blk, 6, 1
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
dwmci_send_cmd: Response Timeout.
Sending CMD55
dwmci_send_cmd: Response Timeout.
Sending CMD0
Sending CMD1
dwmci_send_cmd: Response Timeout.
Card did not respond to voltage select!
spl: mmc init failed with error: -95
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
<debug_uart> 
U-Boot TPL 2020.04 (May 10 2020 - 06:47:07)
spl_early_init
rk3328_dmc_init phy ff400000 pctrl ff780000 grf ff100000 cru ff440000 msch ff720000 ddr_grf ff798000
Starting SDRAM initialization...
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=14 CS=1 Die BW=16 Size=512MB
SPL malloc() before relocation used 0x5e8 bytes (1 KB)
>>TPL: board_init_r()
spl_init
Trying to boot from BOOTROM
Returning to boot ROM...
<debug_uart> 
spl:debug uart enabled in board_init_f
spl_early_init
clk_set_defaults()
clk_set_default_parents: could not read assigned-clock-parents for 3fc030
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: reg-offset: (not found)
ofnode_read_u32: reg-shift: x (2)
ofnode_read_u32: reg-io-width: x (4)
fdtdec_get_int: #clock-cells: x (1)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
PLL at ff440000: fbdiv=75, refdiv=1, postdiv1=3,              postdiv2=1, vco=1800000 khz, output=600000 khz
PLL at ff440060: fbdiv=96, refdiv=1, postdiv1=4,              postdiv2=1, vco=2304000 khz, output=576000 khz
PLL at ff440040: fbdiv=99, refdiv=2, postdiv1=2,              postdiv2=1, vco=1188000 khz, output=594000 khz
clk_set_defaults(clock-controller@ff440000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc2c0
ofnode_read_prop: assigned-clock-rates: <not found>
clk_of_xlate_default(clk=3fbd78)
clk_request(dev=3fc2c0, clk=3fbd78)
clk_get_rate(clk=3fbd78)
ofnode_read_u32: clock-frequency: x (24000000)
clk_set_defaults(serial@ff130000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc1d0
ofnode_read_prop: assigned-clock-rates: <not found>

U-Boot SPL 2020.04 (May 10 2020 - 06:47:07 +0000)
SPL malloc() before relocation used 0xbd0 bytes (2 KB)
>>SPL: board_init_r()
spl_init
board_spl_was_booted_from: brom_bootdevice_id 5 maps to '/rksdmmc@ff500000'
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (4)
ofnode_read_bool: non-removable: false
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff500000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc468
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff0000)
clk_request(dev=3fc2c0, clk=3ff0000)
clk_set_rate(clk=3ff0000, rate=400000)
fdtdec_get_addr_size_auto_parent: na=2, ns=2, fdtdec_get_addr_size_fixed: reg: addr=00000000x
ofnode_read_u32: bus-width: x (8)
ofnode_read_bool: non-removable: true
ofnode_read_u32: fifo-depth: x (256)
ofnode_read_bool: fifo-mode: false
ofnode_read_bool: u-boot,spl-fifo-mode: true
ofnode_read_u32_array: clock-freq-min-max: fdtdec_get_int_array: clock-freq-min-max
get_prop_check_min_len: clock-freq-min-max
ofnode_read_u32: max-frequency: x (150000000)
clk_set_defaults(rksdmmc@ff520000)
clk_set_default_parents: could not read assigned-clock-parents for 3fc790
ofnode_read_prop: assigned-clock-rates: <not found>
fdtdec_get_int: #clock-cells: x (1)
clk_of_xlate_default(clk=3ff00a8)
clk_request(dev=3fc2c0, clk=3ff00a8)
clk_set_rate(clk=3ff00a8, rate=400000)
Trying to boot from MMC1
blk_find_device: if_type=6, devnum=0: rksdmmc@ff500000.blk, 6, 0
clock is disabled (0Hz)
Buswidth = 0, clock: 0
Buswidth = 1, clock: 0
clock is enabled (400000Hz)
Buswidth = 1, clock: 400000
Sending CMD0
Sending CMD8
Sending CMD55
Sending CMD41
Sending CMD55
Sending CMD41
Sending CMD2
Sending CMD3
Sending CMD9
Sending CMD7
Sending CMD55
Sending CMD51
Sending CMD55
Sending CMD6
Buswidth = 4, clock: 400000
clock is enabled (25000000Hz)
Buswidth = 4, clock: 25000000
clk_set_rate(clk=3ff0000, rate=25000000)
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: rksdmmc@ff500000.blk, 6, 0
Sending CMD16
Sending CMD17
dwmci_data_transfer: DATA ERROR!
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
Trying to boot from MMC1
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: rksdmmc@ff500000.blk, 6, 0
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
Trying to boot from MMC2
spl: mmc boot mode: raw
blk_find_device: if_type=6, devnum=0: rksdmmc@ff500000.blk, 6, 0
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
Sending CMD16
dwmci_send_cmd: Response Timeout.
hdr read sector 4000, count=0
mmc_load_image_raw_sector: mmc block read error
spl: mmc boot mode: fs
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

I went through your github repo.

  • The way you have copied the dts and other relevant files by modifying uboot Makefile is completely wrong. Don’t do that. Create a patch and place it inside the patches directory under uboot-rockchip.

  • Same applies to target/rockchip directory for kernel.

  • You’re missing some functional nodes in the device dts. Please refer to raxda github repo: uboot, kernel.

You build seems to fail at uboot.

  • After going through your uboot dts, your build won’t pass u-boot unless activate SPL at uboot for gen3 rk3328 boards. refer to this link.

You’re missing out a lot of the major features in your dts, like the sound node, HDMI node, USB3 nodes and drivers, and probably you’ll also need rockchip-drm for hdmi. Please revise your dts.

Keep up your work and reply here if you need any help. For dts refer to radxa repo.

EDIT: you won’t need HDMI. this board doesn’t seem to have one. Although the AV port is present. Start with a minimal dts and continue adding all the functionalities required, and don’t mess with the voltage regulator nodes.

The way you have copied the dts and other relevant files by modifying uboot Makefile is >completely wrong. Don’t do that. Create a patch and place it inside the patches directory >under uboot-rockchip.

Thanks for your reply,
I know the approach of how to add new target and u-boot support to openwrt. For my repo, it is just for test, since I want to have a look of the image for rockpi-e image quickly. It will pushed to u-boot master as soon as the minimal dts works.

You build seems to fail at uboot.

It does has the problem, you need to install python relevant libraries to avoid build error, please refer to the pull request I referenced previous.

After going through your uboot dts, your build won’t pass u-boot unless activate SPL >at uboot for gen3 rk3328 boards. refer to this link.

Thanks, I will try this approach later.

You’re missing out a lot of the major features in your dts, like the sound node, HDMI >node, USB3 nodes and drivers, and probably you’ll also need rockchip-drm for hdmi. >Please revise your dts.

The key point is the minimal dts file. The sound node, HDMI, USB3 will be added when it boots successful.

I might have seen an patch for rock-pi-e at u-boot mainline, on April mailing list.

refer to my test repo: https://github.com/jayanta525/openwrt-nanopi-r2s/commits/rockpi-e
Also includes lucize PR. The commits are a mess now

Logs provided by @zzl, and seems the board boots with the build i provided. Linux kernel is loaded and that’s enough for an initial testing.

You can also try it: https://github.com/jayanta525/build-openwrt-nanopi-r1/raw/rk3328-nanopi-r2s/rockpi-e-openwrt/openwrt-rockchip-armv8-radxa_rockpi-e-ext4-sysupgrade.img.gz

I have not heard from the testers for a while hence i am unable to progress.

You can proceed without any issues after you apply the uboot patch. For USB3 you will have to create a patch for rk3328.dtsi as well.

I might have seen an patch for rock-pi-e at u-boot mainline, on April mailing list.

Maybe it’s from my private e-mail, I pushed to mainline last month. But the patch is not perfect. It worked with u-boot-no-dtb.bin (must packed with rockchip utility, and booted with rockchip idbloader.img), but I found it boot failed when using idbloader.img and uboot.itb.

refer to my test repo: …
Also includes lucize PR. The commits are a mess now

Logs provided by @zzl, and seems the board boots with the build i provided. Linux >kernel is loaded and that’s enough for an initial testing.

Thanks, will tell you here if this commit works.

1 Like

@jayanta525 it works when apply the patch " [PATCH] rockchip: rk3328: rock64 - fix gen3 SPL hang", thanks

1 Like

UPDATE: 28-07-2020

Updated images with opkg support: https://jayanta525.gitlab.io/openwrt-rockpie/

OpenWrt builds are ready at https://jayanta525.gitlab.io/openwrt-rockchip/
And here: https://wiki.radxa.com/RockpiE/downloads

I will post the procedure on compiling your own image with the sources from openwrt-master. And the link to github repo.

Meanwhile, I am marking this as solved.

Update:

GitHub Repo: https://github.com/jayanta525/rock-pi-e
Currently working on it, will be updated in a few hours.

Just follow the normal procedure of compiling openwrt:

1. git clone --depth 1 https://github.com/jayanta525/rock-pi-e.git openwrt/
2. cd openwrt/
3. ./scripts/feeds update -a
4. ./scripts/feeds install -a
5. make menuconfig
6. make -j$(nproc)

Am I right to assume that the WiFi driver isn’t present in the latest OpenWRT build from jayanta525’s github? I’ve got it installed and there is no sign of the WiFi adapter at all.

Any thoughts on how to install the driver to get WiFi support for the RockPiE?

-Jim