Okay, I finally got myself back to it after making an early first attempt.
I dropped CMSIS as it didn’t appear to support 64-bit.
I went with your code and adjusted it to:
//weird, markdown excludes the “.*” elements from the code markdown below.
.cpu cortex-a55
.global _start
VCCIO3_5_IOC_GPIO4C_PULL_UP_DOWN_ADDRESS = 0xFD5FA148
VCCIO3_5_IOC_GPIO4C_PULL_UP_DOWN_DATA = 0x08001D50
_start:
# move from coprocessor register to arm register
mrs x9, mpidr_el1
# test it
tst x9, 0b11
b.eq . + 0x0c
#
wfe
b.al . - 0x04
# move to x9 register bits
movz x9, :abs_g0_nc:VCCIO3_5_IOC_GPIO4C_PULL_UP_DOWN_ADDRESS
movk x9, :abs_g1:VCCIO3_5_IOC_GPIO4C_PULL_UP_DOWN_ADDRESS
movz w10, :abs_g0_nc:VCCIO3_5_IOC_GPIO4C_PULL_UP_DOWN_DATA
movk w10, :abs_g1:VCCIO3_5_IOC_GPIO4C_PULL_UP_DOWN_DATA
str w10, [x9]
b.al .
Built with: $ aarch64-linux-gnu-gcc -g -mcpu=cortex-a55 -nostdlib <file>.S -o <outFile>.elf
I then objdumped it with: $ aarch64-linux-gnu-objcopy -S -O <inFile>.elf <outFile>.bin
And then packed that bin with [SOLVED] Is there a way to load a program directly into SRAM using USB OTG? - #12 by eystur using $ pack.py rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.11.bin <inFile>.bin <loaderFile>.bin
And finally flashed it with $ rkdeveloptool db <loaderFile>.bin
rkdeveloptool looks to hang, which I guess you already know since you kill it in your Makefile.
Now the purpose of that app is to simply enable the red led, but I’m not sure if I’m even doing that right (obviously not since it doesn’t light up).
The radxa_rock_5b_v142_sch.pdf:p20 shows the red led is located at GPIO4-C5.
While Rockchip RK3588 TRM V1.0-Part1-20220309.pdf shows GPIO4 to be based at FEC50000:p19, I’m guessing I shouldn’t be going that route considering there’s no info on the data fields to go into that address, along with you using “GRF” addresses in your code.
The closest I could find with addresses that relate to manipulating that GPIO is BUS_IOC:p17 and VCCIO3_5_IOC:p17.
Specifically BUS_IOC_GPIO4C_IOMUX_SEL_H:p984 (IOMUX like the GRF*IOMUX in yours) and VCCIO3_5_IOC_GPIO4C_P:p1052.
It doesn’t look like I need to do anything with BUS_IOC_GPIO4C_IOMUX_SEL_H since it defaults to 0x00000000 which sets bits 7:4 to 4'h0: GPIO. So that seems good so far.
I see your code is setting the use of JTAG in your IOMUX, so that’s why you make changes with yours.
Then going to VCCIO3_5_IOC_GPIO4C_P, I see it is GPIO4C Pull-up/down Control:p1029 and defaults to 0x1550. The only thing I’m looking to change here I guess is bit 11 gpio4c5_ps which I set to 1 (1'b1: PU Selection). But that also means I need to change bit 27 to 1 to enable the write to bit 11.
So that changes from the default of 0x1550 to 0x08001D50.
The options are (name; offset; read/write; default; description):
“VCCIO3_5_IOC_GPIO4C_DS_H; 0x0094; W; 0x00000111; GPIO4C Driver Strength Control High bits”:p1041 (2’b01: 7.5mA 33ohm)
“VCCIO3_5_IOC_GPIO4C_P; 0x0148; W; 0x00001550; GPIO4C Pull-up/down Control”:p1052 (1’b0: PD Selection)
“VCCIO3_5_IOC_GPIO4C_P; 0x0148; W; 0x00001550; GPIO4C Pull-up/down Control”:p1052 (1’b1: PU/PD Enable)
“VCCIO3_5_IOC_GPIO4C_IE; 0x01B8; W; 0x0000007C; GPIO4C Input Enable Control”:p1057 (0x1 Active High input buffer enable)
“VCCIO3_5_IOC_GPIO4C_SMT; 0x0248; W; 0x00000000; GPIO4C Schmitt Trigger Control”:p1063 (1’b0: CMOS Input)
But like I said, it doesn’t seem to work (no red led).
So if you or anyone else have an eye for what I may be missing or doing wrong, I’m all ears/eyes.