Just thinking, I’m still having doubts about this. The reason is that when there are limitations somewhere, at least other areas improvements still benefit a little bit (by reducing the cache line fetch time etc), and the curve shouldn’t look like a straight line followed by an immediate plateau. It should normally present a curve around the inflexion point where there are still small improvements that allow to get closer to the internal limit without ever reaching it. Thus I’m suspecting that CIX is just focusing on some known limitations and not necessarily on what is observed. That’s normal to know that a CPU can never use the full DRAM bandwidth, but that’s not the point here, we’re seeing only 40% of the theoretical one. Also, if the limit is due to “internal architectural limitations”, it must still be tied to the frequency of something, be it the core frequency (but here different cores have different frequencies), the DMC frequency, the DDR speed, maybe an internal bus speed, etc. Where is that limitation supposed to happen given that neither CPU cores nor the DDR frequency are involved ? I’m more than willing to have an open (or private if they prefer) discussion with CIX engineers and discussing test methods as well, but I’m still having the feeling that there is some confusion here and that the limit is much lower than what the “internal limitations” should permit.
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